Dram hierarchical data path

Abstract

A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.

1 . A DRAM array comprising: 
 a plurality of rows of DRAM cells, each of said rows being selected by a word line; and    a plurality of columns of said DRAM cells, each of said columns comprising: 
 a plurality of column segments, each of said column segments including DRAM cells in two or more of said plurality of rows connected to a local bit line, a clamp device selectively gated by a hold enable and connected at a conduction terminal to said local bit line and a sense/read device gated by said local bit line, said clamp device being gated off when one of said DRAM cells is selected, and  
 a global bit line connected at a conduction terminal to said sense/read device, contents on each said local bit line being coupled to said global bit line.  
   
   
   
       2 - 4 . (canceled)  
   
   
       5 . A DRAM as in  claim 1 , wherein each said clamp device is connected between said local bit line and a supply line.  
   
   
       6 . A DRAM as in  claim 1 , wherein DRAM is a CMOS DRAM and two or more rows is less than 65 rows.  
   
   
       7 . (canceled)  
   
   
       8 . A DRAM as in  claim 1 , wherein each said read device is connected between said local bit line and a virtual ground.  
   
   
       9 . A DRAM as in  claim 8 , further comprising a virtual ground device connected between each said virtual ground and ground, said virtual ground device selectively connecting said each virtual ground to ground.  
   
   
       10 . A CMOS DRAM macro comprising: 
 a local bit line;    at least two DRAM cells connected to said local bit line;    a clamp device selectively gated by a hold enable and connected at a conduction terminal to said local bit line, said clamp device being gated off when one of said at least two DRAM cells is selected;    a sense/read device gated by said local bit line; and    a global read bit line connected to a conduction terminal of said global read bit line.    
   
   
       11 . A CMOS DRAM as in  claim 10 , wherein the at least two DRAM cells is less than 65 DRAM cells.  
   
   
       12 - 19 . (canceled)  
   
   
       20 . A CMOS DRAM as in  claim 10 , wherein each said read device is connected between said local bit line and a virtual ground.  
   
   
       21 . A CMOS DRAM as in  claim 20 , further comprising a virtual ground device connected between each said virtual ground and ground, said virtual ground device selectively connecting said each virtual ground to ground.  
   
   
       22 . A CMOS logic chip including an embedded DRAM array, said embedded DRAM array comprising: 
 a plurality of rows of DRAM cells, each of said rows being selected by a word line;    a plurality of columns of said DRAM cells, each of said columns including a plurality of column segments, each of said column segments comprising: 
 a local bit line, at least two DRAM cells connected to said local bit line,  
 a clamp device selectively gated by a hold enable and connected at a conduction terminal to said local bit line, said clamp device being gated off when one of said at least two DRAM cells is selected, and  
 a sense/read device gated by said local bit line; and  
   a global read bit line in each column, read devices in said column segments in said each column being connected at a conduction terminal to said global read bit line.    
   
   
       23 . A CMOS logic chip as in  claim 22 , wherein the at least two DRAM cells is less than 65 DRAM cells.  
   
   
       24 - 32 . (canceled)  
   
   
       33 . A DRAM as in  claim 5 , wherein said supply line is a ground line.