US2008009111A1PendingUtilityA1

Manufacturing method of semiconductor device

Assignee: FUJITSU LTDPriority: Jun 14, 2006Filed: Jun 11, 2007Published: Jan 10, 2008
Est. expiryJun 14, 2026(expired)· nominal 20-yr term from priority
H10P 30/222H10D 64/0132H10D 64/021H10D 30/601H10D 84/0184H10D 84/0167H10D 64/017H10D 62/371H10D 30/0227H10D 84/038H10D 84/017H10P 30/221
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Claims

Abstract

A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Claims

exact text as granted — not AI-modified
1 . A manufacturing method of a semiconductor device comprising:
 forming a gate insulating film on a semiconductor substrate,   depositing an amorphous silicon layer on said gate insulating layer,   forming a gate pattern by etching said amorphous silicon layer, and   implanting a first impurity of the same conductivity type as a channel region from a diagonal direction to the surface of said semiconductor substrate using said amorphous silicon layer of said gate pattern as a mask.   
     
     
         2 . The manufacturing method of a semiconductor device according to  claim 1 , wherein said implanting of a first impurity is conducted within a range of 7° to 45° wherein a direction perpendicular to the surface of said semiconductor substrate is defined as 0°. 
     
     
         3 . A manufacturing method of a semiconductor device comprising:
 forming a gate insulating film on a semiconductor substrate;   depositing an amorphous silicon layer on said gate insulating film;   forming a gate pattern by etching said amorphous silicon layer; and   implanting a first impurity of the conductivity type opposite to that of a channel region at a dose of 1×10 14 /cm 2  to 3×10 15 /cm 2  from a diagonal direction to the surface of said semiconductor substrate using said amorphous silicon layer of said gate pattern defined as a mask.   
     
     
         4 . The manufacturing method of semiconductor device according to  claim 1  further comprising:
 converting said amorphous silicon layer of said gate pattern to a polycrystal silicon layer after the step of implanting said first impurity;   wherein said amorphous silicon layer is an impurity-nondoped amorphous silicon layer, and   implanting a second impurity to said polycrystal silicon layer.   
     
     
         5 . The manufacturing method of a semiconductor device according to  claim 4 , wherein the step of converting the amorphous silicon layer into the polycrystal silicon layer is crystallization of the amorphous silicon layer with an annealing process. 
     
     
         6 . The manufacturing method of a semiconductor device according to  claim 4 , wherein the step of converting the amorphous silicon layer into the polycrystal silicon layer is conducted by removing the amorphous silicon layer and depositing the polycrystal silicon layer. 
     
     
         7 . The manufacturing method of a semiconductor device according to  claim 5  further comprising:
 introducing a metal catalyst to said amorphous silicon layer of said gate pattern before the annealing process.   
     
     
         8 . The manufacturing method of a semiconductor device according to  claim 5 , wherein an amorphous layer is formed within said semiconductor substrate by said first impurity during the step of implanting said first impurity. 
     
     
         9 . The manufacturing method of a semiconductor device according to  claim 8 , wherein said annealing process of said amorphous silicon layer is conducted at a temperature allowing said amorphous layer within said semiconductor substrate to remain amorphous. 
     
     
         10 . The manufacturing method of a semiconductor device according to  claim 9 , wherein said annealing is conducted at a temperature within the range from 450° C. to 550° C. 
     
     
         11 . The manufacturing method of a semiconductor device according to  claim 7 , wherein the metal catalyst is Ni or Fe. 
     
     
         12 . The manufacturing method of a semiconductor device according to  claim 3  further comprising:
 converting said amorphous silicon layer of said gate pattern to a polycrystal silicon layer after the step of implanting said first impurity;   wherein said amorphous silicon layer is an impurity-nondoped amorphous silicon layer; and   implanting a second impurity to said polycrystal silicon layer.   
     
     
         13 . The manufacturing method of a semiconductor device according to  claim 12 , wherein the step of converting the amorphous silicon layer into the polycrystal silicon layer is crystallization of the amorphous silicon layer with an annealing process. 
     
     
         14 . The manufacturing method of a semiconductor device according to  claim 12 , wherein the step of converting the amorphous silicon layer into the polycrystal silicon layer is conducted by removing the amorphous silicon layer and depositing the polycrystal silicon layer. 
     
     
         15 . The manufacturing method of a semiconductor device according to  claim 13  further comprising:
 introducing a metal catalyst into said amorphous silicon layer of said gate pattern before the annealing process.   
     
     
         16 . The manufacturing method of a semiconductor device according to  claim 3 , wherein an amorphous layer is formed within said semiconductor substrate by said first impurity during the step of implanting said first impurity. 
     
     
         17 . The manufacturing method of a semiconductor device according to  claim 12 , wherein the metal catalyst is Ni or Fe. 
     
     
         18 . A manufacturing method of a semiconductor device comprising:
 forming a gate insulating film on a semiconductor substrate;   depositing an amorphous, silicon layer on said gate insulating film;   forming a gate pattern by etching said amorphous silicon layer;   depositing an insulating film covering said amorphous silicon layer of said gate pattern;   crystallizing said amorphous silicon layer of said gate pattern with an annealing process; and   forming a side wall spacer on a side wall of said gate pattern by anisotropic etching said insulating film.   
     
     
         19 . The manufacturing method of semiconductor device according to  claim 18  further comprising:
 crystallizing said amorphous silicon layer after the step of forming said side wall spacer.   
     
     
         20 . The manufacturing method of semiconductor device according to  claim 18  further comprising:
 crystallizing said amorphous silicon layer before the step of forming said side wall spacer.

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