Semiconductor devices with shallow trench isolation and methods of fabricating the same

Abstract

A semiconductor device may include a semiconductor substrate that includes first and second regions; first, second, and third insulating layers; a capacitor dielectric layer that includes first and second dielectric layers; a gate insulating layer formed on the first and second regions; a gate formed on the gate insulating layer of the second region; a first capacitor electrode formed on the capacitor dielectric layer; and junction regions formed in the semiconductor substrate on sides of the gate. The first and second regions may include first and second trenches, respectively. The third insulating layer may be formed on the second insulating layer, which may be formed on the first insulating layer, which may be formed on an inner surface of the second trench. The second dielectric layer may be formed on the first dielectric layer, which may be formed on an inner surface of the first trench.

1 . A semiconductor device, comprising:
 a semiconductor substrate that includes first and second regions;   first, second, and third insulating layers;   a capacitor dielectric layer that includes first and second dielectric layers;   a gate insulating layer formed on the first and second regions;   a gate formed on the gate insulating layer of the second region;   a first capacitor electrode formed on the capacitor dielectric layer; and   junction regions formed in the semiconductor substrate on sides of the gate;   wherein the first region includes a first trench having a first depth,   wherein the second region includes a second trench having a second depth,   wherein the first insulating layer is formed on an inner surface of the second trench,   wherein the second insulating layer is formed on the first insulating layer,   wherein the third insulating layer is formed on the second insulating layer,   wherein the first dielectric layer is formed on an inner surface of the first trench, and   wherein the second dielectric layer is formed on the first dielectric layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the first insulating layer includes an oxide layer, and
 wherein the second insulating layer includes a nitride layer.   
   
   
       3 . The semiconductor device of  claim 1 , wherein a portion of the gate insulating layer functions as a third dielectric layer of the capacitor dielectric layer. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the first insulating layer and the first dielectric layer include a first material. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the second insulating layer and the second dielectric layer include a second material. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the gate and the first capacitor electrode include a third material. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the semiconductor substrate functions as a second capacitor electrode. 
   
   
       8 . The semiconductor device of  claim 7 , wherein a ground voltage is applied to the semiconductor substrate, and
 wherein a power voltage is applied to the first capacitor electrode.   
   
   
       9 . The semiconductor device of  claim 7 , further comprising:
 a first metal interconnection electrically connected to the first capacitor electrode;   a second metal interconnection electrically connected to the semiconductor substrate;   a third metal interconnection electrically connected to the gate; and   a fourth metal interconnection electrically connected to one of the junction regions.   
   
   
       10 . The semiconductor device of  claim 1 , further comprising:
 a first well formed in the first region; and   a second well formed in the second region;   wherein the first well has a first junction depth greater than the first depth of the first trench, and   wherein the second well has a second junction depth greater than the second depth of the second trench.   
   
   
       11 . The semiconductor device of  claim 10 , wherein the first well functions as a second capacitor electrode. 
   
   
       12 . The semiconductor device of  claim 10 , wherein the first junction depth is greater than or equal to the second junction depth. 
   
   
       13 . The semiconductor device of  claim 10 , wherein the first and second wells are both p-type wells, or
 wherein the first and second wells are both n-type wells.   
   
   
       14 . The semiconductor device of  claim 10 , further comprising:
 a contact region formed in the first region;   wherein the contact region is spaced apart from the first trench, and   wherein the contact region and the first well have a same conductivity type.   
   
   
       15 . The semiconductor device of  claim 11 , further comprising:
 a first metal interconnection electrically connected to the first capacitor electrode;   a second metal interconnection electrically connected to the first well;   a third metal interconnection electrically connected to the gate; and   a fourth metal interconnection electrically connected to one of the junction regions.   
   
   
       16 . The semiconductor device of  claim 15 , wherein when the first well is a p-type well, a power voltage is applied to the first metal interconnection and a ground voltage is applied to the second metal interconnection, and
 wherein when the first well is an n-type well, the ground voltage is applied to the first metal interconnection and the power voltage is applied to the second metal interconnection.   
   
   
       17 . The semiconductor device of  claim 1 , wherein a bottom of the first trench includes one or more stripe-shaped recesses extending in a same direction. 
   
   
       18 . The semiconductor device of  claim 1 , wherein a bottom of the first trench includes one or more mesh-shaped recesses. 
   
   
       19 . A method of fabricating a semiconductor device, the method comprising:
 preparing a semiconductor substrate that includes first and second regions;   etching the semiconductor substrate to form a first trench, having a first depth, in the first region and a second trench, having a second depth, in the second region;   forming first, second, and third insulating layers in the second trench;   forming a capacitor dielectric layer that includes first and second dielectric layers in the first trench;   forming a gate insulating layer on the first and second regions;   forming a gate on the gate insulating layer of the second region;   forming a first capacitor electrode on the capacitor dielectric layer; and   forming junction regions in the semiconductor substrate on sides of the gate.   
   
   
       20 . The method of  claim 19 , wherein a bottom of the first trench includes one or more stripe-shaped recesses extending in a same direction. 
   
   
       21 . The method of  claim 19 , wherein a bottom of the first trench includes one or more mesh-shaped recesses. 
   
   
       22 . The method of  claim 19 , wherein the first insulating layer includes an oxide layer, and
 wherein the second insulating layer includes a nitride layer.   
   
   
       23 . The method of  claim 19 , wherein the semiconductor substrate functions as a second capacitor electrode. 
   
   
       24 . The method of  claim 23 , wherein at least portions of the first dielectric layer, the second dielectric layer, and the gate insulating layer that are disposed between the first and second capacitor electrodes form an oxide-nitride-oxide (ONO) structure of the capacitor dielectric layer. 
   
   
       25 . The method of  claim 23 , the method further comprising, after forming the junction regions:
 forming a first metal interconnection electrically connected to the first capacitor electrode;   forming a second metal interconnection electrically connected to the semiconductor substrate;   forming a third metal interconnection electrically connected to the gate; and   forming a fourth metal interconnection electrically connected to one of the junction regions.   
   
   
       26 . The method of  claim 19 , the method further comprising, before forming the first and second trenches:
 forming a first well in the first region; and   forming a second well in the second region;   wherein the first well has a first junction depth greater than the first depth of the first trench,   wherein the second well has a second junction depth greater than the second depth of the second trench,   wherein the first trench is formed in the first well, and   wherein the second trench is formed in the second well.   
   
   
       27 . The method of  claim 19 , the method further comprising, after forming the first and second trenches, but before forming the first insulating layer, the first dielectric layer, or the first insulating layer and the first dielectric layer:
 forming a first well in the first region; and   forming a second well in the second region;   wherein the first well has a first junction depth greater than the first depth of the first trench,   wherein the second well has a second junction depth greater than the second depth of the second trench,   wherein the first trench is formed in the first well, and   wherein the second trench is formed in the second well.   
   
   
       28 . The method of  claim 19 , the method further comprising, after forming the first, second, and third insulating layers and the capacitor dielectric layer, but before forming the gate insulating layer:
 forming a first well in the first region; and   forming a second well in the second region;   wherein the first well has a first junction depth greater than the first depth of the first trench,   wherein the second well has a second junction depth greater than the second depth of the second trench,   wherein the first trench is formed in the first well, and   wherein the second trench is formed in the second well.   
   
   
       29 . The method of  claim 28 , wherein the first well functions as a second capacitor electrode. 
   
   
       30 . The method of  claim 29 , wherein at least portions of the first dielectric layer, the second dielectric layer, and the gate insulating layer that are disposed between the first and second capacitor electrodes form an oxide-nitride-oxide (ONO) structure of the capacitor dielectric layer. 
   
   
       31 . The method of  claim 19 , wherein forming the junction regions comprises:
 forming a contact region in the first region;   wherein the contact region is spaced apart from the first trench, and   wherein the contact region and the first well have a same conductivity type.   
   
   
       32 . The method of  claim 29 , the method further comprising, after forming the junction regions:
 forming a first metal interconnection electrically connected to the first capacitor electrode;   forming a second metal interconnection electrically connected to the first well;   forming a third metal interconnection electrically connected to the gate; and   forming a fourth metal interconnection electrically connected to one of the junction regions.   
   
   
       33 . A method of fabricating a semiconductor device, the method comprising:
 preparing a semiconductor substrate that includes first and second regions;   etching the semiconductor substrate to form a first trench, having a first depth, in the first region and a second trench, having a second depth, in the second region;   forming a first fabricating layer in the first and second trenches;   forming a second fabricating layer on the first fabricating layer and the semiconductor substrate;   forming a third fabricating layer on the second fabricating layer;   etching the second and third fabricating layers to form first and second dielectric layers and an isolation layer in the first trench, and first, second, and third insulating layers in the second trench;   removing the isolation layer;   forming a gate insulating layer on the first and second regions;   forming a gate on the gate insulating layer of the second region;   forming a first capacitor electrode on the gate insulating layer of the first region; and   forming junction regions in the semiconductor substrate on sides of the gate.