Semiconductor device having recess gate and method of fabricating the same

Abstract

A semiconductor device having a recess gate includes a semiconductor substrate having a recess, a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate, an epitaxial semiconductor layer having a top surface disposed over the semiconductor substrate, and a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern. Further, a method of fabricating the same is disclosed.

1 . A semiconductor device having a recess gate, comprising:
 a semiconductor substrate having a recess;   a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate;   an epitaxial semiconductor layer having a top surface disposed over the semiconductor substrate; and   a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the semiconductor substrate and the epitaxial semiconductor layers comprise silicon. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the recess is shallow so that the conductive pattern can be formed in a single step to avoid forming a seam in the conductive pattern. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the conductive pattern comprises polysilicon. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the thickness of the epitaxial semiconductor layer is at least approximately 100 Å. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a gate electrode over the conductive pattern, wherein the gate electrode comprises at least one of a metal pattern and a metal silicide pattern. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a gate electrode over the conductive pattern, wherein the gate electrode comprises at least one of a tungsten pattern and a tungsten silicide pattern. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the gate insulating layer further comprises:
 a first oxide layer disposed between the semiconductor substrate and the conductive pattern; and   a second oxide layer disposed between the epitaxial semiconductor layer and the conductive pattern.   
     
     
         9 . A method of fabricating a semiconductor device having a recess gate, the method comprising:
 forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface;   forming a first gate insulating layer on a surface of the recess;   forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate;   forming a second gate insulating layer on side surfaces of the extension portion of the conductive pattern; and   epitaxially growing a semiconductor layer over the semiconductor substrate to a top surface of the conductive pattern.   
     
     
         10 . The method of  claim 9 , wherein forming the conductive pattern for the gate electrode further comprises:
 depositing a conductive layer over the resultant structure where the first gate insulating layer is formed;   pattering the conductive layer using a gate mask and etching process to form the conductive pattern; and   performing a light etch treatment for rounding corners of the conductive pattern.   
     
     
         11 . The method of  claim 9 , further comprising, after epitaxially growing the semiconductor layer, planarizing the semiconductor layer. 
     
     
         12 . The method of  claim 9 , wherein forming the conductive pattern further comprises forming the conductive pattern in a single step to avoid a seam forming in the conductive pattern. 
     
     
         13 . The method of  claim 11 , wherein forming the second gate insulating layer on the side surfaces of the extension portion further comprises:
 forming an oxide layer over the resultant structure including the conductive pattern; and   anisotropically etching the oxide layer.   
     
     
         14 . The method of  claim 9 , wherein forming the conductive pattern further comprising forming the conductive pattern comprising polysilicon. 
     
     
         15 . The method of  claim 11 , wherein planarizing the semiconductor layer further comprises planarizing the semiconductor layer using a chemical mechanical polishing (CMP) process. 
     
     
         16 . The method of  claim 9 , wherein forming a recess in a semiconductor substrate further comprises forming a recess in a semiconductor substrate, wherein the semiconductor substrate comprises silicon; and wherein epitaxially growing a semiconductor layer further comprises epitaxially growing a semiconductor layer, wherein the semiconductor layer comprises silicon. 
     
     
         17 . The method of  claim 9 , further comprising forming a pattern over the conductive pattern, wherein the pattern comprises at least one of a metal pattern and a metal silicide pattern. 
     
     
         18 . A method of fabricating a semiconductor device having a recess gate, the method comprising:
 forming a recess in a semiconductor substrate, wherein the semiconductor substrate has a top surface;   forming a first gate insulating layer on a surface of the recess; and   forming a conductive pattern for a gate electrode, wherein the conductive pattern fills the recess, and has an extension portion protruding higher than the top surface of the semiconductor substrate.   
     
     
         19 . The method of  claim 18 , wherein forming the conductive pattern further comprising depositing a conductive layer in a single step to avoid a seam forming in the conductive layer, wherein the conductive pattern is formed by etching the conductive layer. 
     
     
         20 . The method of  claim 18 , wherein forming the conductive pattern for the gate electrode further comprises:
 depositing a conductive layer over the resultant structure where the first gate insulating layer is formed;   pattering the conductive layer using a gate mask and etching process to form the conductive pattern; and   performing a light etch treatment for rounding corners of the conductive pattern.   
     
     
         21 . A semiconductor device having a recess gate, comprising:
 a semiconductor substrate having a recess; and   a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the recess is shallow so that the conductive pattern can be formed in a single step to avoid forming a seam in the conductive pattern. 
     
     
         23 . The semiconductor device of  claim 21 , wherein the conductive pattern has rounded corners.