Self-aligned element isolation film structure in a flash cell and forming method thereof

Abstract

A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

1 . A self-aligned element isolation film structure in a flash memory cell, comprising: 
 a floating gate pattern on a semiconductor substrate with an insulating layer therebetween; and    an element isolation film, grown in a self-aligned manner at a side of the floating gate pattern with a thickness larger than that of the insulating layer to fill a space between adjacent floating gates.    
   
   
       2 . The self-aligned element isolation film structure in the flash memory cell of  claim 1 , wherein the floating gate pattern comprises a polysilicon film.  
   
   
       3 . The self-aligned element isolation film structure in a flash memory cell of  claim 1 , wherein the element isolation film comprises an oxide film.  
   
   
       4 . The flash memory cell of  claim 3 , wherein the element isolation film comprises a thermal oxide.  
   
   
       5 . The flash memory cell of  claim 1 , wherein the insulating layer comprises a tunnel dielectric layer.  
   
   
       6 . The flash memory cell of  claim 1 , further comprising an ion implantation region in a portion of the substrate not covered by the floating gate pattern.  
   
   
       7 . The flash memory cell of  claim 1 , further comprising a control gate on or over the floating gate.  
   
   
       8 . A flash memory cell, comprising: 
 a floating gate pattern on a semiconductor substrate with an insulating layer therebetween, the floating gate pattern comprising a plurality of floating gates; and    a self-aligned element isolation film at sides of the floating gate pattern having a thickness greater than that of the insulating layer to fill a space between adjacent floating gates.    
   
   
       9 . The flash memory cell of  claim 8 , wherein the floating gate pattern comprises a polysilicon film.  
   
   
       10 . The flash memory cell of  claim 8 , wherein the element isolation film comprises an oxide film.  
   
   
       11 . The flash memory cell of  claim 10 , wherein the element isolation film comprises a thermal oxide.  
   
   
       12 . The flash memory cell of  claim 8 , wherein the insulating layer comprises a tunnel dielectric layer.  
   
   
       13 . The flash memory cell of  claim 8 , further comprising an ion implantation region in a portion of the substrate not covered by the floating gate pattern.  
   
   
       14 . The flash memory cell of  claim 8 , further comprising a control gate on or over the floating gate.