Apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device

Abstract

An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.

1 . A method, in an integrated circuit device, for identifying a faulty module of the integrated circuit device, comprising:
 applying an input test pattern to a plurality of modules of the integrated circuit device, wherein the plurality of modules are copies of one another within a manufacturing tolerance;   sampling, within the integrated circuit device, internal signals of at least two modules in the plurality of modules;   comparing, within the integrated circuit device, the internal signals of the at least two modules to detect if there is any discrepancy between the internal signals; and   identifying the integrated circuit device as faulty if a discrepancy between the internal signals is detected by the comparison.   
     
     
         2 . The method of  claim 1 , wherein sampling internal signals comprises sampling the internal signals using internal signal sampling logic built into each of the at least two modules in the plurality of modules, and wherein comparing the internal signals of the at least two modules comprises using comparison logic built into at least one of the at least two modules in the plurality of modules. 
     
     
         3 . The method of  claim 1 , wherein identifying the integrated circuit device as faulty comprises:
 providing results of the comparison to a trace/debug bus of the integrated circuit device;   transferring the results of the comparison to a trace logic analyzer provided on the integrated circuit device via the trace/debug bus; and   analyzing, in the trace logic analyzer, the results of the comparison to determine if the integrated circuit device is faulty.   
     
     
         4 . The method of  claim 1 , wherein comparing the internal signals of the at least two modules comprises:
 comparing, in a first comparison, one or more internal signals of a first module with one or more internal signals of a second module; and   comparing, in a second comparison, the one or more internal signals of the first module with one or more internal signals of a third module.   
     
     
         5 . The method of  claim 4 , wherein the first module and second module are opposite each other with respect to a bus of the integrated circuit device, and wherein the first module and third module are adjacent to each other with respect to the bus of the integrated circuit device. 
     
     
         6 . The method of  claim 4 , further comprising identifying which module in the plurality of modules on the integrated circuit device is faulty based on results of the first comparison and second comparison. 
     
     
         7 . The method of  claim 6 , wherein if results of the first comparison indicate a faulty module and results of the second comparison indicate a faulty module, then the first module is identified as the faulty module. 
     
     
         8 . The method of  claim 6 , further comprising:
 performing a hot-swap operation to swap a spare module for the faulty module identified by the results of the first comparison and second comparison.   
     
     
         9 . The method of  claim 1 , wherein the plurality of modules are processors and the integrated circuit device is a multiprocessor integrated circuit device. 
     
     
         10 . The method of  claim 9 , wherein the multiprocessor integrated circuit device is a heterogeneous multiprocessor system-on-a-chip having a control processor and a plurality of co-processors, and wherein the plurality of co-processors constitute the plurality of modules. 
     
     
         11 . An apparatus, comprising:
 a plurality of modules, wherein the plurality of modules are copies of one another within a manufacturing tolerance;   internal signal sampling logic provided in each of the plurality of modules; and   comparison logic provided in each of the plurality of modules, wherein:   an input test pattern is applied to the plurality of modules of the integrated circuit device,   the internal signal sampling logic of at least two modules in the plurality of modules samples internal signals of the at least two modules,   the comparison logic of at least one module of the at least two modules compares the internal signals of the at least two modules to detect if there is any discrepancy between the internal signals, and   the integrated circuit device is identified as faulty if a discrepancy between the internal signals is detected by the comparison logic of the at least one module.   
     
     
         12 . The apparatus of  claim 11 , wherein the comparison logic of a first module comprises an exclusive OR gate that compares an output signal of an adjacent second module with an internal signal of the first module. 
     
     
         13 . The apparatus of  claim 11 , further comprising:
 a trace/debug bus coupled to the plurality of modules; and   a trace logic analyzer coupled to the trace/debug bus, wherein the integrated circuit device is identified as faulty by:   providing results of the comparison to the trace/debug bus;   transferring the results of the comparison to the trace logic analyzer via the trace/debug bus; and   analyzing, in the trace logic analyzer, the results of the comparison to determine if the integrated circuit device is faulty.   
     
     
         14 . The apparatus of  claim 11 , wherein the internal signals of the at least two modules are compared by:
 comparing, in a first comparison, one or more internal signals of a first module with one or more internal signals of a second module; and   comparing, in a second comparison, the one or more internal signals of the first module with one or more internal signals of a third module.   
     
     
         15 . The apparatus of  claim 14 , wherein the first module and second module are opposite each other with respect to a bus of the apparatus, and wherein the first module and third module are adjacent to each other with respect to the bus of the apparatus. 
     
     
         16 . The apparatus of  claim 14 , wherein one of a trace logic analyzer or external testing equipment identifies which module in the plurality of modules of the apparatus is faulty based on results of the first comparison and second comparison. 
     
     
         17 . The apparatus of  claim 16 , wherein if results of the first comparison indicate a faulty module and results of the second comparison indicate a faulty module, then the first module is identified as the faulty module. 
     
     
         18 . The apparatus of  claim 16 , wherein one of the trace logic analyzer or the external testing equipment initiates a hot-swap operation to swap a spare module for the faulty module identified by the results of the first comparison and second comparison. 
     
     
         19 . The apparatus of  claim 11 , wherein the plurality of modules are processors and the apparatus is a multiprocessor integrated circuit device. 
     
     
         20 . The apparatus of  claim 19 , wherein the multiprocessor integrated circuit device is a heterogeneous multiprocessor system-on-a-chip having a control processor and a plurality of co-processors, and wherein the plurality of co-processors constitute the plurality of modules.