DMA module and operating system therefor

Abstract

A DMA module is described which, in order to read or write a memory location within a DMA process, accesses by a reading operation a memory location of an addressable memory ( 5 ) identified by a first address ( 46 ) in order to read there at least one second address ( 52 ); which advances the second address ( 52 ) to an adjacent memory location, and implements a write access or read access at a memory location identified by the second address ( 52 ); and which finally stores the second address at the memory location identified by the first address ( 46 ).

1 . A method of operating a DMA module, comprising the steps: 
 a) implementing a read access to a memory location of an addressable memory ( 5 ) identified by a first address in order to read there at least one second address ( 52 );    b) in any order: advancing the second address ( 52 ) to an adjacent memory location and storing the second address ( 52 ) at the memory location identified by the first address;    c) implementing a write or read access at a memory location identified by the second address ( 52 ).    
     
     
         2 . The method of  claim 1 , characterized in that before each implementation of step b) a count value ( 53 ) is read, that the count value ( 53 ) is decremented or incremented and re-stored after implementation of step b), and that the method halts when the count value has reached a predetermined final value.  
     
     
         3 . The method of  claim 2 , characterized in that the count value ( 53 ) is recorded during each read access of step a), and logged during each write access of step b).  
     
     
         4 . The method of  claim 1 , characterized in that the write access or read access takes place within one cycle of a bus ( 8 ) through which the DMA module ( 4 ) is connected to the memory ( 5 ).  
     
     
         5 . The method of  claim 4 , characterized in that the DMA module ( 4 ) halts a microcontroller ( 1 ) also connected to the memory ( 5 ) within a bus cycle in which the module accesses the memory ( 5 ).  
     
     
         6 . The method of  claim 1 , including the step in which a DMA access is requested by a peripheral module, and the first address is selected based on the identity of the peripheral module.  
     
     
         7 . The method of  claim 6 , characterized in that the peripheral module requests the DMA access through its interrupt request line.  
     
     
         8 . The method of  claim 6 , characterized in that the interrupt request is suppressed in response to the triggering of the DMA access through the interrupt request line.