Nonvolatile semiconductor memory with backing wirings and manufacturing method thereof

Abstract

A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st gate electrode of a 1st memory cell transistor formed on a 1st region of a semiconductor substrate through a 1st insulating layer and a 3rd gate electrode of a 2nd memory cell transistor formed on a 2nd region through the 1st insulating layer. The (b) is a step of forming a 1st hard mask layer which covers a bottom portion and a side surface of a concave portion formed using the gate film between the 1st gate electrode and the 3rd gate electrode by etching the hard mask film. The (c) is a step of forming a 2nd gate electrode of the 1st memory cell transistor on the 1st region, a 4th gate electrode of the 2nd memory cell transistor on the 2nd region, and a connection layer which connects the 2nd gate electrode and the 4th gate electrode under the 1st hard mask layer by etching the gate film. The (d) is a step of exposing upper portions of the 1st gate electrode, the 3rd gate electrode and the connection layer by etching back the 2nd insulating film and the 1st hard mask layer covering a bottom portion of the concave portion to remain the 1st hard mask layer such that the 1st hard mask layer covers side surfaces of the concave portion.

1 . A manufacturing method of a nonvolatile semiconductor memory comprising:
 (a) laminating a second insulating film, a gate film and a hard mask film which cover a first gate electrode of a first memory cell transistor formed on a first region of a semiconductor substrate through a first insulating layer and a third gate electrode of a second memory cell transistor formed on a second region of said semiconductor substrate through said first insulating layer;   (b) forming a first hard mask layer which covers a bottom portion and a side surface of a concave portion formed using said gate film between said first gate electrode and said third gate electrode by etching said hard mask film; and   (c) forming a second gate electrode of said first memory cell transistor on said first region, a fourth gate electrode of said second memory cell transistor on said second region, and a connection layer which connects said second gate electrode and said fourth gate electrode under said first hard mask layer by etching said gate film; and   (d) exposing upper portions of said first gate electrode, said third gate electrode and said connection layer by etching back said second insulating film and said first hard mask layer covering a bottom portion of said concave portion to remain said first hard mask layer such that said first hard mask layer covers side surfaces of said concave portion.   
     
     
         2 . The manufacturing method of a nonvolatile semiconductor memory according to  claim 1 , further comprising:
 (e) forming a silicide layer in an upper portion of said connection layer.   
     
     
         3 . The manufacturing method of a nonvolatile semiconductor memory according to  claim 1 , further comprising:
 (f) forming sidewall insulating film which covers said second gate electrode of said first memory cell transistor and said fourth gate electrode of said second memory cell transistor.   
     
     
         4 . The manufacturing method of a nonvolatile semiconductor memory according to  claim 1 , further comprising:
 (g) forming an isolation region in said first region and said second region of a surface portion of said semiconductor substrate.   
     
     
         5 . The manufacturing method of a nonvolatile semiconductor memory according to  claim 1 , wherein said step (a) includes:
 (a1) laminating said second insulating film, said gate film and said hard mask film which cover a fifth gate electrode of a third memory cell transistor formed on a third region of said semiconductor substrate through said first insulating layer and a seventh gate electrode of a fourth memory cell transistor formed on a fourth region of said semiconductor substrate through said first insulating layer,   said step (b) includes:   (b1) forming a second hard mask layer which covers a bottom portion and a side surface of said concave portion formed using said gate film between said fifth gate electrode and said seventh gate electrode by etching said hard mask film,   said step (c) includes:   (c1) removing said second hard mask layer by etching, and   (c2) forming a sixth gate electrode of said third memory cell transistor on said third region, and a eighth gate electrode of said fourth memory cell transistor on said fourth region by etching said gate film,   said step (d) includes:   (d1) exposing upper portions of said fifth gate electrode and said seventh gate electrode by etching back said second insulating film,   wherein said sixth gate electrode and said eighth are isolated to each other,   said first gate electrode and said fifth gate electrode, said second gate electrode and said sixth gate electrode, said third gate electrode and said seventh gate electrode, and, said fourth gate electrode and said eighth gate electrode are unified, respectively.   
     
     
         6 . The manufacturing method of a nonvolatile semiconductor memory according to  claim 1 , wherein said step (c) includes:
 (c3) forming two of said second gate electrodes on both sides of said first gate electrode and two of said fourth gate electrodes on both sides of said third gate electrode.   
     
     
         7 . A nonvolatile semiconductor memory includes:
 a first memory cell transistor configured to includes:
 a first gate electrode configured to be formed above a first channel region, and 
 a second gate electrode configured to be formed on a side of said first gate electrode through an insulating film; 
   a second memory cell transistor configured to includes:
 a third gate electrode configured to be formed above a second channel region, and 
 a fourth gate electrode configured to be formed on a side of said third gate electrode through an insulating film and faced to said second gate electrode; 
   a connection layer configured to connect said second gate electrode and said fourth gate electrode;   protrusion portions configured to be formed on both ends of said connection layer; and   a contact portion configured to be formed on said connection layer and be coupled with a metal wiring.   
     
     
         8 . The nonvolatile semiconductor memory according to  claim 7 , wherein said connection layer includes:
 a silicide layer configured to be formed at the connecting portion with said contact portion.   
     
     
         9 . The nonvolatile semiconductor memory according to  claim 8 , wherein upper and side surfaces of said second gate electrode and said protrusion portion in a side of said second gate electrode is covered with a sidewall insulating film of said first gate electrode, and
 upper and side surfaces of said fourth gate electrode and said protrusion portion in a side of said fourth gate electrode is covered with a sidewall insulating film of said third gate electrode.   
     
     
         10 . The nonvolatile semiconductor memory according to  claim 7 , wherein said first memory cell transistor and said second memory cell transistor are formed on an isolation layer. 
     
     
         11 . The nonvolatile semiconductor memory according to  claim 7 , further comprising:
 a third memory cell transistor configured to includes:
 a fifth gate electrode configured to be formed above a third channel region, and 
 a sixth gate electrode configured to be formed on a side of said fifth gate electrode through an insulating film; and 
   a fourth memory cell transistor configured to includes:
 a seventh gate electrode configured to be formed above a fourth channel region, and 
 a eighth gate electrode configured to be formed on a side of said seventh gate electrode through an insulating film and faced to said sixth gate electrode, 
   wherein said sixth gate electrode and said eighth are isolated to each other,   said first gate electrode and said fifth gate electrode, said second gate electrode and said sixth gate electrode, said third gate electrode and said seventh gate electrode, and, said fourth gate electrode and said eighth gate electrode are unified, respectively.   
     
     
         12 . The nonvolatile semiconductor memory according to  claim 7 , wherein said first memory cell transistor includes:
 two of said second gate electrodes on both sides of said first gate electrode,   said second memory cell transistor includes:   two of said fourth gate electrodes on both sides of said third gate electrode.