Field effect transistor device with channel fin structure and method of fabricating the same

Abstract

A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.

1 . A method of fabricating a field effect transistor (FET) device having a channel fin structure, the method comprising: 
 providing a semiconductor substrate having a specific region;    etching the semiconductor substrate to form a trench surrounding the specific region;    filling the trench with a trench-insulating layer;    opening recess holes within the specific region such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes:    forming gate lines that overlie and extend across the channel fins; and    forming source/drain regions at both ends of the channel fins.    
   
   
       2 . The method of  claim 1 , wherein etching the semiconductor substrate comprises etching the substrate to form the trench comprises etching the semiconductor substrate to form a trench having a cross-sectional profile shaped like a rectangle, a reverse triangle, or a reverse trapezoid.  
   
   
       3 . The method of  claim 1 , wherein filling the trench with the trench-insulating layer comprises filling the trench with an oxide.  
   
   
       4 . The method of  claim 1 , wherein opening recess holes to form channel fins comprises opening recess holes to form channel fins having a cross-sectional profile shaped like a pointed triangle, a rectangle, or a trapezoid.  
   
   
       5 . The method of  claim 1 , wherein forming gate lines comprises sequentially stacking gate dielectric layers, gate electrodes, and stopper layers on the substrate.  
   
   
       6 . The method of  claim 1 , wherein forming gate lines comprises filling the recess holes with the gate lines.  
   
   
       7 . A method of fabricating a field effect transistor (FET) device having a channel fin structure, the method comprising: 
 providing a semiconductor substrate having a specific region;    covering the specific region with a mask block;    forming a spacer on a sidewall of the mask block;    etching a trench in the semiconductor substrate using the mask block as an etch mask;    filling the trench with a trench-insulating layer;    removing the mask block from the semiconductor substrate;    forming mask lines on the semiconductor substrate such that the mask lines cross over the spacer;    etching a recess hole within the specific region of the semiconductor substrate using the mask lines and the spacer as an etch mask such that channel fins are formed from raised portions of the semiconductor substrate disposed on sides of the recess hole;    removing the mask lines and the spacer such that the channel fins are exposed;    forming gate lines that overlie and extend across the channel fins; and    forming source/drain regions at ends of the channel fins.    
   
   
       8 . The method of  claim 7 , wherein covering the specific region with a mask block comprises: 
 depositing, in sequence, a nitride layer and an anti-reflection coating layer on the semiconductor substrate; and    patterning the nitride layer and the anti-reflection coating layer.    
   
   
       9 . The method of  claim 8 , wherein covering the specific region with a mask block further comprises depositing an oxide layer on the semiconductor substrate before depositing the nitride layer.  
   
   
       10 . The method of  claim 8 , wherein covering the specific region with a mask block further comprises etching the patterned nitride layer in a lateral direction.  
   
   
       11 . The method of  claim 9 , wherein removing the mask block comprises removing, in sequence, the anti-reflective coating layer and the nitride layer while leaving the oxide layer on the semiconductor substrate.  
   
   
       12 . The method of  claim 8 , wherein removing the mask block comprises: 
 removing upper parts of the spacer and the anti-reflective coating layer by a chemical mechanical polishing process; and    removing the nitride layer by using etchant.    
   
   
       13 . The method of  claim 9 , wherein etching the recess hole comprises etching the oxide layer by using the mask lines and the spacer as an etch mask.  
   
   
       14 . The method of  claim 9 , wherein removing the mask lines and the spacer comprises removing the oxide layer.  
   
   
       15 . The method of  claim 7 , wherein forming the spacer comprises: 
 coating the mask block with an insulating material; and    etching-back the insulating material.    
   
   
       16 . The method of  claim 7 , wherein the mask block has a rectangular flat shape in a plan view.  
   
   
       17 . The method of  claim 7 , wherein the mask lines are spaced apart from each other such that the spacer is partly exposed therebetween.