Nonvolatitle memory array and method for operating thereof

Abstract

A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.

1 . A nonvolatile memory cell comprising:
 a substrate;   a doped region located in the substrate, wherein the doped region has a conductive type and the doped region extends from a top surface of the substrate toward to a bottom of the substrate; and   a gate structure located on the substrate and across the doped region, wherein the gate structure comprises a multi-carrier storage element on the doped region and a gate on the multi-carrier storage element and the multi-carrier storage element comprises at least two carrier storage spaces including a first carrier storage space and a second carrier storage space, wherein the first carrier storage space and the second carrier storage space are located adjacent to the multi-carrier storage element at both side of the doped region respectively and there is no buried diffusion oxide layer structure over the substrate and the gate structure has complete the multi-carrier storage element.   
   
   
       2 . The nonvolatile memory cell of  claim 1 , wherein, during a programming process is performed on the nonvolatile memory cell, the doped region further comprises a first inversion region in a portion of the doped region covered by the gate structure. 
   
   
       3 . The nonvolatile memory cell of  claim 2 , wherein the conductive type of the first inversion region is different from that of the doped region. 
   
   
       4 . The nonvolatile memory cell of  claim 1 , wherein, during a reading process is performed on the nonvolatile memory cell:
 when the first storage space of the multi-carrier storage element stores at least one carrier, the doped region further comprises a second inversion region located in a portion of the doped region covered by a portion of the gate structure other than the first carrier storage space; and   when there is no carrier stored in the multi-carrier storage element, the doped region has a third inversion region located in a portion of the doped region covered by the gate structure.   
   
   
       5 . The nonvolatile memory cell of  claim 4 , wherein the second inversion region and the third inversion region possess the same conductive type and the conductive types of the second inversion region and the third inversion region are different from the conductive type of the doped region. 
   
   
       6 . The nonvolatile memory cell of  claim 1 , wherein, during an erasing process is performed on the nonvolatile memory cell, the doped region has a fourth inversion region in a portion of the doped region covered by the gate structure. 
   
   
       7 . The nonvolatile memory cell of  claim 6 , wherein the conductive type of the fourth inversion region is different from that of the doped region. 
   
   
       8 . The nonvolatile memory cell of  claim 1 , wherein a thickness of the doped region is of about 200 angstroms. 
   
   
       9 . The nonvolatile memory cell of  claim 1 , wherein the multi-carrier storage element comprises an oxide/nitride/oxide layer. 
   
   
       10 . The nonvolatile memory cell of  claim 1 , wherein there is at least one nonvolatile memory cell in a two-feature-size square region. 
   
   
       11 . The nonvolatile memory cell of  claim 1 , wherein a gate pitch size of the gate structure is smaller than a feature size. 
   
   
       12 . A mixed nonvolatile memory array having a plurality of mixed type memory cell, comprising:
 a substrate having a first conductive type, wherein the substrate possesses at least two doped regions including a first doped region and a second doped region, the first doped region and the second doped region extend from a top surface of the substrate toward to a bottom of the substrate, the first doped region and the second doped region are parallel to each other and the first doped region and the second doped region possesses a second conductive type; and   at least a gate structure located on the substrate and across the doped regions and possessing a plurality of carrier storage spaces, wherein the gate structure, the first doped region and the second doped region together form a mixed type memory cell and the mixed type memory cell comprises:
 an enhanced mode memory cell composed of the gate structure, a portion of the first doped region covered by the gate structure and a portion of the second doped region covered by the gate structure; and 
 a depletion mode memory cell composed of the first doped region and the gate structure. 
   
   
   
       13 . The mixed nonvolatile memory array of  claim 12 , wherein, during a programming process is performed on the depletion mode memory cell, the first doped region has a first inversion region located in a portion of the first doped region covered by the gate structure and the conductive type of the first inversion region is different from that of the first doped region. 
   
   
       14 . The mixed nonvolatile memory array of  claim 12 , wherein, during a reading process is performed on the depletion mode memory cell:
 when the depletion mode memory cell is at a carrier storage state, the first doped region possesses a second inversion region covered by a portion of the gate structure other than the carrier storage spaces, which store at least one carrier, and the conductive type of the second inversion region is different from that of the first doped region; and   when the depletion mode memory cell is at a non-carrier storage state, the first doped region has a third inversion region covered by the gate structure and the conductive type of the third inversion region is different from that of the first doped region.   
   
   
       15 . The mixed nonvolatile memory array of  claim 12 , wherein, during an erasing process is performed on the depletion mode memory cell, the first doped region has a fourth inversion region covered by the gate structure and the conductive type of the fourth inversion region is different from that of the first doped region. 
   
   
       16 . The mixed nonvolatile memory array of  claim 12 , wherein a thickness of each of the doped regions is of about 200 angstroms. 
   
   
       17 . The mixed nonvolatile memory array of  claim 12 , wherein when the first conductive type is P type, the second conductive type is N type; when the first conductive type is N type, the second conductive type is P type. 
   
   
       18 . The mixed nonvolatile memory array of  claim 12 , wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element. 
   
   
       19 . The mixed nonvolatile memory array of  claim 18 , wherein the multi-carrier storage element includes an oxide/nitride/oxide layer. 
   
   
       20 . The mixed nonvolatile memory array of  claim 12 , wherein the enhanced mode memory cell comprises a first carrier storage space and a second carrier storage space located at a portion of the gate structure between the first doped region and the second doped region, the first carrier storage space is adjacent to the first doped region and the second carrier storage space is adjacent to the second doped region. 
   
   
       21 . The mixed nonvolatile memory array of  claim 12 , wherein the depletion mode memory cell comprises a third carrier storage space and a fourth carrier storage space located in both sides of the gate structure covering the first doped region and adjacent to the first doped region respectively. 
   
   
       22 . The mixed nonvolatile memory array of  claim 12 , wherein there is at least one mixed type memory cell in a two-feature-size square region. 
   
   
       23 . The mixed nonvolatile memory array of  claim 12 , wherein a gate pitch size of the gate structure is smaller than a feature size. 
   
   
       24 . The mixed nonvolatile memory array of  claim 12 , wherein the gate structure further comprises a complete multi-carrier storage element having the carrier storage spaces. 
   
   
       25 . A method for programming a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising:
 during the enhanced mode memory cell is programmed, applying a first voltage on the gate structure to turn on a channel region having the second conductive type in the substrate under the gate structure between the first doped region and the second doped region and applying a first bias between the first doped region and the second doped region to inject a plurality of electrons into the gate structures in a way of channel hot carrier; and   during the depletion mode memory cell is programmed, applying a second voltage on the gate structure to invert a conductive type of a portion of the first doped region under the gate structure from the second conductive type into the first conductive type and applying a second bias on the first doped region to inject a plurality of holes into the gate structures in a way of band-to-band tunneling hot carrier.   
   
   
       26 . The method of  claim 25 , wherein a thickness of the first doped region is of about 200 angstroms and a thickness of the second doped region is of about 200 angstroms. 
   
   
       27 . The method of  claim 25 , wherein when the first conductive type is P type and the second conductive type is N type, the channel hot carrier includes a channel hot electron process and the band-to-band tunneling hot carrier includes a band-to-band tunneling hot hole process. 
   
   
       28 . The method of  claim 25 , wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element. 
   
   
       29 . The method of  claim 28 , wherein the multi-carrier storage element includes an oxide/nitride/oxide layer. 
   
   
       30 . A method for reading a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising:
 during the enhanced mode memory cell is read, applying a first voltage on the gate structure to turn on a channel region having the second conductive type in the substrate under the gate structure between the first doped region and the second doped region and applying a first bias between the first doped region and the second doped region to read the enhanced mode memory cell in a way of reverse read; and   during the depletion mode memory cell is read, applying a second voltage on the gate structure to invert a conductive type of a portion of the first doped region under the gate structure from the second conductive type into the first conductive type and applying a second bias on the first doped region to read the depletion mode in the way of reverse read.   
   
   
       31 . The method of  claim 30 , wherein a thickness of the first doped region is of about 200 angstroms and a thickness of the second doped region is of about 200 angstroms. 
   
   
       32 . The method of  claim 30 , wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element. 
   
   
       33 . The method of  claim 32 , wherein the multi-carrier storage element includes an oxide/nitride/oxide layer. 
   
   
       34 . A method for erasing a nonvolatile memory array having a plurality of memory cells, wherein each memory cell includes a first doped region of a second conductive type and a second doped region of the second conductive type located in a substrate of a first conductive type and parallel to and adjacent to each other, each memory cell further includes a gate structure located on the substrate and across the first doped region and the second doped region, the first doped region and the gate structure together form a depletion mode memory cell and the first doped region, the second doped region and the first gate structure together form an enhanced mode memory cell, and method comprising:
 during the enhanced mode memory cell is erased, applying a first voltage on the gate structure and grounding the first doped region and the second doped region to erase the enhanced mode memory cell in a way of Flowler-Nordheim tunneling effect; and   during the depletion mode memory cell is erased, applying a second voltage on the gate structure and grounding the first doped region to erase the depletion mode in the way of Flowler-Nordheim tunneling effect.   
   
   
       35 . The method of  claim 34 , wherein a thickness of the first doped region is of about 200 angstroms and a thickness of the second doped region is of about 200 angstroms. 
   
   
       36 . The method of  claim 34 , wherein the gate structure comprises a multi-carrier storage element located on the substrate and a gate located on the multi-carrier storage element. 
   
   
       37 . The method of  claim 36 , wherein the multi-carrier storage element includes an oxide/nitride/oxide layer. 
   
   
       38 . The method of  claim 34 , wherein, when the enhanced mode memory cell and the depletion mode memory cell are erased at the same time, the first voltage is equal to the second voltage.