Mram with a write driver and a method therefor

Abstract

Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell. The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures. To avoid this deleterious saturation, the magnetic field is reduced during the time when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.

1 .- 6 . (canceled)  
     
     
         7 . A method of writing a memory cell of an MRAM, wherein the memory cell has a synthetic antiferromagnet (SAF) layer that can be saturated by a magnetic field of sufficient magnitude applied to the memory cell, comprising: 
 applying a first magnetic field and a second magnetic field to the memory cell at different times; and    applying the first magnetic field and the second magnetic field to the memory cell during an overlap time wherein a vector sum of the first magnetic field and the second magnetic field during the overlap time is lower than the sufficient magnitude.    
     
     
         8 . The method of  claim 7 , wherein the first magnetic field and the second magnetic field are applied by passing current through conductors in the memory cell.  
     
     
         9 . The method of  claim 7 , wherein the applying the first magnetic field and the second magnetic field to the memory cell at different times comprises: 
 applying the first magnetic field at a first level prior to the overlap time; and    applying the second magnetic field at a second level after the overlap time.    
     
     
         10 . The method of  claim 9 , wherein the first level exceeds the vector sum, and the vector sum exceeds the second level.  
     
     
         11 . An MRAM, comprising: 
 an MRAM array comprising a plurality of MRAM cells; and    a write driver for writing a memory cell of the plurality of MRAM cells;    wherein the write driver comprises: 
 a first driver coupled to the memory cell for passing a first portion of a first current through a first current path of the memory cell;  
 a second driver coupled to the memory cell that passes a second portion of the first current through the first current path;  
 a third driver coupled to the memory cell for passing a first portion of a second current through a second current path;  
 a fourth driver coupled to the memory cell for passing a second portion of the second current through the second current path; and  
 a select circuit that enables the first driver and the second driver during a first time period, the first driver during a second time period, the third driver and the fourth driver during a third time period, and the third driver during the second time period.  
   
     
     
         12 . The MRAM of  claim 11 , wherein the first driver comprises a first plurality of transistors connected in parallel, and the second driver comprises a second plurality of transistors connected in parallel with the first plurality of transistors.  
     
     
         13 . The MRAM of  claim 12 , wherein the third driver comprises a third plurality of transistors connected in parallel, and the fourth driver comprises a fourth plurality of transistors connected in parallel with the third plurality of transistors.  
     
     
         14 . The MRAM of  claim 11 , wherein the select circuit comprises: 
 a first select circuit coupled to the first driver and the second driver; and    a second select circuit coupled to the third driver and the fourth driver.    
     
     
         15 . The MRAM of  claim 14 , wherein the first select circuit comprises: 
 a bias circuit;    a logic circuit; and    an output stage coupled to the bias circuit, the logic circuit, the first driver, and the second driver.    
     
     
         16 . The MRAM of  claim 15 , wherein the logic circuit comprises: 
 a first logic gate having a first input for receiving a first pulse, a second input for receiving an enable signal, and an output coupled to the output stage; and    a second logic gate having a first input for receiving a second pulse, a second input for receiving the enable signal, and an output coupled to the output stage.    
     
     
         17 . The MRAM of  claim 15 , wherein the output stage comprises: 
 a first pair of transistors connected in series coupled to the logic circuit and the first driver; and    a second pair of transistors connected in series coupled to the logic circuit and the second driver.    
     
     
         18 . The MRAM of  claim 14 , wherein the first select circuit comprises a current mirror coupled to the first driver and the second driver and sets a bias for the first driver and the second driver.  
     
     
         19 . The MRAM of  claim 18 , wherein the first select circuit couples a first pulse to the first driver and a second pulse to the second driver.  
     
     
         20 . The MRAM of  claim 19  wherein the current mirror is enabled by an enable signal.