Semiconductor device having silicide thin film and method of forming the same

Abstract

The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

1 . A semiconductor device, comprising: 
 a gate insulation layer on an active region of a semiconductor substrate;    a gate electrode on the gate insulation layer;    a lightly-doped impurity region in the active region at both sides of the gate electrode;    a first spacer on sidewalls of the gate electrode and on at least a portion of the lightly-doped impurity region, wherein the first spacer is L-shaped and comprises silicon oxide;    a second spacer on the first spacer, the second spacer comprising silicon nitride;    a heavily-doped impurity region in the active region at both sides adjacent to the second spacer;    a first cobalt silicide layer on the heavily-doped impurity region;    a second cobalt silicide layer on the gate electrode, wherein a top surface of the second cobalt silicide layer is higher than a top surface of the first spacer and a top surface of the second spacer; and    a subsidiary layer covering the first cobalt silicide layer, the second cobalt silicide layer, the first spacer and the second spacer, wherein the subsidiary layer has a higher oxygen concentration in a lower portion thereof contacting the first cobalt silicide layer and the second cobalt silicide layer than in another portion of the subsidiary layer not contacting the first cobalt silicide layer and the second cobalt silicide layer.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the subsidiary layer comprises silicon oxynitride.  
   
   
       3 . The semiconductor device according to  claim 1 , further comprising an interlayer insulating layer on the subsidiary layer.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein a thickness of the first cobalt silicide layer and a thickness of the second cobalt silicide layer are different.  
   
   
       5 . The semiconductor device according to  claim 4 , wherein the second cobalt silicide layer is thicker than the first second cobalt silicide layer.  
   
   
       6 . The semiconductor device according to  claim 1 , wherein the lower portion of the subsidiary layer includes oxygen provided from the first cobalt silicide layer and the second cobalt silicide layer.  
   
   
       7 . The semiconductor device according to  claim 1 , wherein the second cobalt silicide layer does not contact the second spacer.  
   
   
       8 . The semiconductor device according to  claim 1 , wherein a lower surface of the second cobalt silicide layer is higher than the top surface of the first spacer and the top surface of the second spacer.  
   
   
       9 . A semiconductor device, comprising: 
 a gate insulation layer on an active region of a semiconductor substrate;    a gate electrode on the gate insulation layer;    an impurity region in the active region, extending outwardly from both sides of the gate electrode;    a first spacer on both sides of the gate electrode and on the impurity region, wherein the first spacer is L-shaped;    a second spacer on the first spacer;    a first cobalt silicide layer on the impurity region, the first cobalt silicide layer being disposed at a height lower than a bottom surface of the second spacer;    a second cobalt silicide layer on the gate electrode, wherein a top surface of the second cobalt silicide layer is higher than a top surface of the first spacer and a top surface of the second spacer; and    a subsidiary layer covering the first cobalt silicide layer, the second cobalt silicide layer, the first spacer and the second spacer, wherein a portion of the subsidiary layer facing toward the first cobalt silicide layer and the second cobalt silicide layer has a higher oxygen concentration than a portion of the subsidiary layer facing away from the first cobalt silicide layer and the second cobalt silicide layer.    
   
   
       10 . The semiconductor device according to  claim 8 , wherein the second cobalt silicide layer does not contact the second spacer.  
   
   
       11 . The semiconductor device according to  claim 8 , wherein a lower surface of the second cobalt silicide layer is higher than the top surface of the first spacer and the top surface of the second spacer.  
   
   
       12 . A semiconductor device, comprising: 
 a gate insulation layer on a semiconductor substrate;    a gate electrode on the gate insulation layer;    an impurity region in the semiconductor substrate and at both sides of the gate electrode, the impurity region including a lightly-doped region and a heavily-doped region;    a first spacer on both sides of the gate electrode and above at least a portion of the lightly doped region, wherein the first spacer comprises a first portion and a second portion connected together to form an L-shape;    a second spacer covering a region of the first spacer wherein the first portion and the second portion are connected together;    a first cobalt silicide layer on top of at least a portion of the heavily doped region;    a second cobalt silicide layer on top of the gate electrode, wherein at least a portion of the second cobalt silicide layer is located at a height above the first spacer and the second spacer; and    a subsidiary layer covering the first cobalt silicide layer, the second cobalt silicide layer, the first spacer and the second spacer.    
   
   
       13 . The semiconductor device according to  claim 11 , wherein the subsidiary layer has a higher oxygen concentration in a portion contacting the first cobalt silicide layer and the second cobalt silicide layer in comparison to a portion not contacting the first cobalt silicide layer and the second cobalt silicide layer.  
   
   
       14 . The semiconductor device according to  claim 11 , wherein the second cobalt silicide layer does not contact the second spacer.