Self-driven ldmos transistor

Abstract

The present invention provides a self-driven LDMOS, which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal will be clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS will be turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention doesn't lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential doesn't vary in response to an increment of the drain-voltage potential.

What is claimed is: 
     
         1 . A structure of a voltage-controlled transistor, comprising a voltage-control terminal, a source terminal, and a drain terminal; wherein a voltage potential at said voltage-control terminal varies in response to a voltage variation at said drain terminal; said voltage potential at said voltage-control terminal being controlled to be clipped at a predetermined voltage potential when a pinch-off situation of said voltage-controlled transistor occurs; wherein when said voltage potential at said voltage-control terminal exceeds said predetermined voltage potential, said voltage potential at said voltage-control terminal is no longer varied in response to a drain-voltage potential at said drain terminal; wherein a discontinuous polarity distribution structure is formed between said drain terminal and said voltage-control terminal; said voltage-control terminal is connected to an auxiliary region having the same doping polarity as said drain terminal; wherein said drain-voltage potential controls two depletion boundaries; and wherein when said two depletion boundaries pinch off, said voltage potential at said voltage-control terminal is controlled to be clipped at said predetermined voltage potential. 
     
     
         2 . The structure as claimed in  claim 1 , wherein said voltage-controlled transistor is turned on whenever said voltage-control terminal is controlled to be clipped at said predetermined voltage potential. 
     
     
         3 . The structure as claimed in  claim 1 , wherein a complementary doping region is disposed between said drain terminal and said voltage-control terminal of said voltage-controlled transistor, wherein a doping polarity of said complementary doping region is complementary to that of said drain terminal of said voltage-controlled transistor. 
     
     
         4 . The structure as claimed in  claim 1 , wherein said discontinuous polarity distribution structure is comprised of a doping region with complementary doping polarity to that of said drain terminal, wherein said doping region is in parallel to a conduction channel of said voltage-control transistor and facilitates said two depletion boundaries to pinch off. 
     
     
         5 . A structure of a voltage-controlled transistor, utilizing a bias voltage to vary two depletion boundaries resulted from complementary ions, wherein a resistance of a parasitic resistor between a drain terminal and a voltage-control terminal of said voltage-controlled transistor varies in response to said two depletion boundaries controlled by a drain-voltage potential at said drain terminal, and wherein a voltage potential at said voltage-control terminal is clipped at said drain-voltage potential at said drain terminal when said two depletion boundaries pinch off. 
     
     
         6 . The structure as claimed in  claim 5 , wherein said voltage-controlled transistor is turned on when said voltage potential at said voltage-control terminal is clipped at a predetermined voltage potential. 
     
     
         7 . An LDMOS, comprising a drain, a gate, and a source, wherein a quasi-linked doping region connects said drain and said gate, said quasi-linked doping region having a discontinuous polarity distribution structure is in parallel to a conduction channel of said LDMOS. 
     
     
         8 . The LDMOS as claimed in  claim 7 , further comprising a first complementary doping region with complementary doping polarity to that of said drain, said first complementary doping region being disposed between said drain and said gate. 
     
     
         9 . The LDMOS as claimed in  claim 7 , further comprising a second complementary doping region with complementary doping polarity to that of said drain, said second complementary doping region being coupled to an edge of said gate in said quasi-linked doping region. 
     
     
         10 . The LDMOS as claimed in  claim 7 , wherein a doping concentration of said quasi-linked doping region ranges from 1.7E17/cm 3  to 8.3E18/cm 3 . 
     
     
         11 . The LDMOS as claimed in  claim 7 , wherein a depth of said quasi-linked doping region ranges from 2 μm to 10 μm. 
     
     
         12 . The LDMOS as claimed in  claim 7 , wherein a width of said discontinuous polarity distribution structure in said quasi-linked doping region is between 0 μm and 20 μm. 
     
     
         13 . The LDMOS as claimed in  claim 7 , wherein a gate oxide layer disposed under said gate has a thickness ranging from 300 Å to 1000 Å. 
     
     
         14 . The LDMOS as claimed in  claim 8 , wherein a doping concentration of said first complementary doping region ranges from 3.3E17/cm 3  to 1E19/cm 3 . 
     
     
         15 . The LDMOS as claimed in  claim 8 , wherein a depth of said first complementary doping region ranges from 1 μm to 5 μm. 
     
     
         16 . A process for manufacturing a voltage-controlled transistor, comprising steps of:
 providing a substrate;   forming a quasi-linked deep well in said substrate;   forming a well with complementary doping polarity to that of said quasi-linked deep well in said substrate;   forming an oxide layer over said substrate for serving as isolation structures;   forming a gate-oxide layer over said quasi-linked deep well;   forming heavy doping regions in said quasi-linked deep well; and   forming a conductor for connecting a gate of said voltage-controlled transistor and said quasi-linked deep well.   
     
     
         17 . The process as claimed in  claim 16 , wherein the step of forming said quasi-linked deep well further comprises a step of performing a thermal driving process under 1000° C.˜1200° C. for 6˜12 hours. 
     
     
         18 . The process as claimed in  claim 16 , wherein the step of forming said well with complementary doping polarity to that of said quasi-linked deep well further comprises performing a thermal driving process under 900° C.˜1100° C. for 2˜6 hours.