Integrated Circuit Including a Memory Cell Array

Abstract

An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.

1 . An integrated circuit including a memory cell array, comprising: 
 a plurality of memory cells, each memory cell including a transistor;    bit lines oriented in a first direction;    word lines oriented in a second direction, the second direction intersecting the first direction; and    a semiconductor substrate comprising active area lines formed therein, a longer side of each active area line extending in the second direction;    wherein transistors of the memory cells are at least partially formed in the active area lines,    wherein the transistors comprise gate electrodes, each of the gate electrodes being connected with one of the word lines, and    wherein each gate electrode includes a bottom side, each word line includes a bottom side, the bottom side of the gate electrodes being disposed under the bottom side of the word lines, and the word lines are disposed over the bit lines.    
     
     
         2 . The integrated circuit of  claim 1 , wherein each gate electrode is disposed in a groove, the groove extending in a direction perpendicular to the substrate surface.  
     
     
         3 . The integrated circuit of  claim 1 , wherein the memory cell further comprises: 
 a trench capacitor including: 
 a first capacitor electrode;  
 a second capacitor electrode; and  
 a dielectric layer disposed between the first and second capacitor electrodes, the first and second capacitor electrodes and the dielectric layer being disposed in a trench extending in the semiconductor substrate.  
   
     
     
         4 . The integrated circuit of  claim 1 , wherein the transistors further comprise: 
 gate contacts, each of the gate contacts connecting a respective gate electrode to a corresponding word line.    
     
     
         5 . The integrated circuit of  claim 1 , further comprising: 
 an insulating spacer electrically insulating the gate electrode from first and second source/drain regions of the transistor, the insulating spacer extending perpendicularly with respect to the semiconductor substrate surface.    
     
     
         6 . The integrated circuit of  claim 1 , wherein a channel of the transistor connecting first and second source/drain regions of the transistor includes vertical portions and a horizontal portion with respect to the substrate surface, the horizontal portion being adjacent to the bottom side of the gate electrode.  
     
     
         7 . The integrated circuit of  claim 6 , wherein the horizontal portion of the channel includes a region doped with a dopant of a conductivity type of the channel at a higher concentration than a dopant concentration of the channel.  
     
     
         8 . The integrated circuit of  claim 6 , wherein one of the vertical portions of the channel includes a region doped with a dopant of a conductivity type of the channel at a higher concentration than a dopant concentration of the channel, the doped region being approximate the second source/drain region.  
     
     
         9 . The integrated circuit of  claim 1 , wherein the word lines comprise metal.  
     
     
         10 . The integrated circuit of  claim 1 , wherein a current path of the electrical current flow between first and second source/drain regions of the transistor includes, in sequence, a vertical component, a horizontal component, and another vertical component.  
     
     
         11 . An integrated circuit including a memory cell array, comprising; 
 a plurality of memory cells, each memory cell including a transistor;    bit lines oriented in a first direction;    word lines oriented in a second direction, the second direction intersecting the first direction; and    a semiconductor substrate comprising active area lines formed therein, each active area extending in the second direction;    wherein transistors of the memory cells are at least partially formed in the active area lines,    wherein the transistors comprise gate electrodes, each of the gate electrodes being connected with one of the word lines, and    wherein each gate electrode includes a bottom side, each word line includes a bottom side, the bottom side of the gate electrodes being disposed under the bottom side of the word lines, and wherein an upper surface of each of the word lines is disposed over an upper surface of each of the bit lines.    
     
     
         12 . An integrated circuit including a memory cell array, comprising: 
 active area lines formed in a semiconductor substrate; and    a plurality of memory cells, each memory cell including a transistor, the memory cells being at least partially formed in the active area lines, individual ones of the transistors including: 
 first and second source/drain regions;  
 a channel region extending between the first and second source/drain regions, the channel region including vertical portions and a horizontal portion with respect to a surface of the semiconductor substrate, wherein the horizontal portion of the channel includes a region doped with a dopant of a conductivity type of the channel region at a higher concentration than a dopant concentration of other regions of the channel region; and  
 a gate electrode disposed along the channel region and configured to control an electrical current flowing between the first and second source/drain regions, wherein the horizontal portion of the channel region is adjacent to a bottom side of the gate electrode.  
   
     
     
         13 . An integrated circuit including a memory cell array, comprising: 
 a plurality of memory cells, each memory cell including a transistor;    bit lines oriented in a first direction;    word lines oriented in a second direction intersecting the first direction;    a semiconductor substrate comprising a plurality of active area lines formed therein, a longer side of each active area line extending in the second direction such that the active area lines are parallel to the word lines, wherein the transistors of the memory cells are at least partially formed in the active area lines, individual ones of the transistors including: 
 a gate electrode coupled to a respective word line.  
   
     
     
         14 . An integrated circuit including a memory cell array, comprising: 
 a plurality of memory cells, each memory cell including a transistor;    bit lines oriented in a first direction;    word lines oriented in a second direction intersecting the first direction;    a semiconductor substrate comprising a plurality of active area lines formed therein, wherein the transistors of the memory cells are at least partially formed in the active area lines, individual ones of the transistors including: 
 a gate electrode coupled to a respective word line, wherein an upper surface of each of the word lines is disposed over an upper surface of each of the bit lines.