System and Method for Using a Plurality of Heterogeneous Processors in a Common Computer System

Abstract

A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.

1 . A method for handling a plurality of heterogeneous processors that share a common memory, said method comprising: 
 identifying a memory size requirement that corresponds to a first processor, the first processor adapted to process a first instruction set;    configuring the common memory in response to the identification;    determining whether there is unassigned memory located on the common memory after the configuration; and    assigning the unassigned memory to a second processor, the second processor adapted to process a second instruction set.    
   
   
       2 . The method as described in  claim 1  wherein the first processor is a Power PC and wherein the second processor is a synergistic processing unit.  
   
   
       3 . The method as described in  claim 1  further comprising: 
 managing the common memory using a common memory map.    
   
   
       4 . The method as described in  claim 3  wherein one of the first processors includes an operating system whereby the first processor controls the common memory map.  
   
   
       5 . The method as described in  claim 3  wherein the common memory map includes a plurality of regions, wherein at least one of the regions is selected from the group consisting of an external system memory region, a local storage aliases region, a TLB region, an MFC region, an operating system region, and an I/O devices region.  
   
   
       6 . The method as described in  claim 1  wherein at least one of the second processors uses a direct memory access controller for accessing the common memory.  
   
   
       7 . A computer program product stored on a computer operable media for handling a plurality of heterogeneous processors that share a common memory, said computer program product comprising: 
 means for identifying a memory size requirement that corresponds to a first processor, the first processor adapted to process a first instruction set;    means for configuring the common memory in response to the identification;    means for determining whether there is unassigned memory located on the common memory after the configuration; and    means for assigning the unassigned memory to a second processor, the second processor adapted to process a second instruction set.    
   
   
       8 . The computer program product as described in  claim 7  wherein the first processor is a Power PC and wherein the second processor is a synergistic processing unit.  
   
   
       9 . The computer program product as described in  claim 7  further comprising: 
 means for managing the common memory using a common memory map.    
   
   
       10 . The computer program product as described in  claim 9  wherein one of the first processors includes an operating system whereby the first processor controls the common memory map.  
   
   
       11 . The computer program product as described in  claim 9  wherein the common memory map includes a plurality of regions, wherein at least one of the regions is selected from the group consisting of an external system memory region, a local storage aliases region, a TLB region, an MFC region, an operating system region, and an I/O devices region.  
   
   
       12 . The computer program product as described in  claim 7  wherein at least one of the second processors uses a direct memory access controller for accessing the common memory.