Method, system and medium for controlling semiconductor wafer processes using critical dimension measurements

Abstract

Methods, systems, and mediums of controlling a semiconductor manufacturing process are described. The method comprises the steps of measuring at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, determining at least one process parameter value on the at least one measured dimension, and controlling at least one semiconductor manufacturing tool to process the at least one of the plurality of wafers based on the at least one parameter value. A variation in the at least one critical dimension causes undesirable variations in performance of the at least one device, and at least one process condition is directed to controlling the processing performed on the plurality of wafers. The at least one manufacturing tool includes at least one of an implanter tool and an annealing tool.

1 . A semiconductor wafer processing module comprising: 
 a first metrology tool configured to measure at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;    a second metrology tool configured to measure at least one post process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is junction depth;    a module controller configured to determine at least one parameter value based on the at least one measured dimension or the at least one post process dimension; and    a plurality of semiconductor manufacturing tools, configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one parameter value, wherein the manufacturing tools include at least two implanter tools, and    wherein each implanter tool is configured for implanting ions into a junction of the at least one device for at least reducing deviation in gate delay.    
   
   
       2 . A method of processing a plurality of wafers for manufacturing semiconductor devices, the method comprising: 
 (a) measuring at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;    (b) determining at least one parameter value based on the at least one measured dimension;    (c) controlling at least one semiconductor processing tool to process the at least one of the plurality of wafers based on the at least one parameter value, wherein the at least one manufacturing tool includes at least one implanter tool for implanting ions into a junction of said at least one device for at least reducing deviation in gate delay; and    (d) measuring at least one process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is junction depth.    
   
   
       3 . A semiconductor wafer processing system comprising: 
 a first metrology tool configured to measure at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;    a module controller configured to determine at least one parameter value based on the at least one measured dimension;    a first semiconductor processing tool configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one parameter value, wherein the first manufacturing tool includes at least one implanter tool for implanting ions into a junction of said at least one device for at least reducing deviation in gate delay; and    a second metrology tool configured to measure at least one post process dimension of the at least one of the plurality of wafers.    
   
   
       4 . A semiconductor wafer processing system comprising: 
 a first metrology tool configured to measure at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;    a second metrology tool configured to measure at least one post process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is junction depth;    a module controller configured to determine at least one parameter value based on the at least one measured dimension or the at least one post process dimension; and    an implanter tool configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one parameter value, to thereby reduce deviation in gate delay.    
   
   
       5 . A semiconductor wafer processing system comprising: 
 a first metrology tool configured to measure at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;    a module controller configured to determine at least one parameter value based on the at least one measured dimension;    a second metrology tool configured to measure at least one post process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is junction depth; and    an annealing tool configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one parameter value, to thereby reduce deviation in gate delay.