Trench isolation structures for integrated circuits

Abstract

A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.

1 . A method of fabricating trench isolation structures between integrated electrical devices in a semiconductor substrate, comprising: 
 placing a semiconductor substrate in a reaction chamber, the semiconductor substrate comprising trenches; and    filling the trenches with silicon oxide by an atomic layer deposition process comprising a plurality of deposition cycles, each deposition cycle comprising, in sequence: 
 introducing a first vapor-phase reactant comprising a silicon source gas to the substrate, thereby forming no more than about one monolayer of a first reactant species conforming at least to surfaces of the trenches;  
 removing excess first vapor-phase reactant and byproduct from the reaction chamber;  
 introducing a second vapor-phase reactant comprising an oxidant source gas to the substrate; and  
 removing excess second vapor-phase reactant and byproduct from the reaction chamber.  
   
   
   
       2 . The method of  claim 1 , wherein filling the trenches comprises repeating the deposition cycles until the trenches are filled.  
   
   
       3 . The method of  claim 2 , wherein repeating comprises conducting the deposition cycles until no space remains within the trenches.  
   
   
       4 . The method of  claim 1 , wherein the oxidant source gas comprises ozone.  
   
   
       5 . The method of  claim 1 , wherein the oxidant source gas comprises water.  
   
   
       6 . The method of  claim 1 , wherein the silicon source gas comprises an organic silicon compound.  
   
   
       7 . The method of  claim 1 , wherein the silicon source gas comprises an aminoalkyltrialkoxysilane.  
   
   
       8 . The method of  claim 1 , wherein the silicon source gas comprises a silicon halide.  
   
   
       9 . The method of  claim 1 , wherein the silicon source gas comprises a silicon halosilane.  
   
   
       10 . The method of  claim 1 , wherein the silicon source gas is selected from the group consisting of SiCl 4 , DCS, SiH 2 Cl 2 , TCS and SiHCl 3 .  
   
   
       11 . The method of  claim 1 , wherein during filling the substrate is maintained at a temperature of between about 150° C. and 400° C.  
   
   
       12 . The method of  claim 11 , wherein during filling the substrate is maintained at a temperature of between about 200° C. and 300° C.  
   
   
       13 . The method of  claim 1 , wherein during filling the reaction chamber is maintained at a pressure from about 3 Torr and 50 Torr.  
   
   
       14 . The method of  claim 1 , wherein the trenches are narrower than about 100 nm.  
   
   
       15 . The method of  claim 1 , wherein the trenches are narrower than about 70 nm.  
   
   
       16 . The method of  claim 1 , wherein the aspect ratio of the trenches is greater than about 5:1.  
   
   
       17 . A method of fabricating trench isolation structures in a semiconductor substrate, comprising: 
 placing a semiconductor substrate comprising trenches in a reaction chamber; and    filling the trenches with silicon oxide by alternately and sequentially contacting the substrate with vapor phase pulses of a silicon source gas and an oxidant source gas.    
   
   
       18 . The method of  claim 17 , wherein the trenches are narrower than about 100 nm.  
   
   
       19 . The method of  claim 17 , wherein prior to contacting the substrate with vapor phase pulses, further comprising preparing the trenches with a surface treatment to provide a desired termination.  
   
   
       20 . The method of  claim 17 , further comprising continuously flowing a carrier gas during filling.  
   
   
       21 . The method of  claim 20 , wherein the carrier gas is an inactive carrier gas.  
   
   
       22 . The method of  claim 17 , wherein the oxidant source gas comprises water vapor.  
   
   
       23 . An ALD process for filling trench isolation structures on a substrate comprising sequentially and alternately contacting a substrate with vapor phase pulses of a silicon source gas and an oxidant source gas at least until the trench isolation structures are completely filled.  
   
   
       24 . The process of  claim 23 , further comprising planarizing the trench isolation structures after the trench isolation structures are completely filled.  
   
   
       25 . The process of  claim 24 , wherein planarizing the trench isolation structures comprises chemical mechanical polishing.