Graphics processing architecture employing a unified shader

Abstract

A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

1 . A method comprising: 
 performing vertex manipulation operations and pixel manipulation operations by transmitting to a general purpose register block, vertex data and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and    continuing pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.    
   
   
       2 . A unified shader, comprising: 
 a general purpose register block for maintaining data;    a processor unit;    a sequencer, coupled to the general purpose register block and the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in the general purpose register block; and    wherein the processor unit executes instructions that generate a pixel color in response to the selected one of the plurality of inputs and generates vertex position and appearance data in response to a selected one of the plurality of inputs.    
   
   
       3 . A unified shader comprising: 
 a processor unit operative to perform vertex calculation operations and pixel calculation operations; and    shared resources, operatively coupled to the processor unit;    the processor unit operative to use the shared resources for either vertex data or pixel information and operative to perform pixel calculation operations until enough shared resources become available and then use the shared resources to perform vertex calculation operations.    
   
   
       4 . A unified shader comprising: 
 a processor unit operative to perform vertex calculation operations and pixel calculation operations; and    shared resources, operatively coupled to the processor unit;    the processor unit operative to use the shared resources for either vertex data or pixel information and operative to perform vertex calculation operations until enough shared resources become available and then use the shared resources to perform pixel calculation operations.    
   
   
       5 . A unified shader comprising: 
 a processor unit;    a sequencer coupled to the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in a store depending upon an amount of space available in the store.    
   
   
       6 . The shader of  claim 5 , wherein the sequencer further includes circuitry operative to fetch data from a memory.  
   
   
       7 . The shader of  claim 5 , further including a selection circuit operative to provide information to the store in response to a control signal.  
   
   
       8 . The shader of  claim 5 , wherein the processor unit executes instructions that generate a pixel color in response to the selected one of the plurality of inputs.  
   
   
       9 . The shader of  claim 5 , wherein the processor unit executes vertex calculations while the pixel calculations are still in progress.  
   
   
       10 . The shader of  claim 5 , wherein the processor unit generates vertex position and appearance data in response to a selected one of the plurality of inputs.  
   
   
       11 . The shader of  claim 7 , wherein the control signal is provided by an arbiter.  
   
   
       12 . A graphics processor comprising: 
 a unified shader comprising a processor unit that executes vertex calculations while the pixel calculations are still in progress.    
   
   
       13 . The graphics processor of  claim 12  wherein the unified shader comprises a sequencer coupled to the processor unit, the sequencer maintaining instructions operative to cause the processor unit to execute vertex calculation and pixel calculation operations on selected data maintained in a store depending upon an amount of space available in the store.  
   
   
       14 . The graphics processor of  claim 12  comprising a vertex block operative to fetch vertex information from memory.  
   
   
       15 . A unified shader comprising: 
 a processor unit flexibly controlled to perform vertex manipulation operations and pixel manipulation operations based on vertex or pixel workload.    
   
   
       16 . The shader of  claim 15  comprising an instruction store and wherein the processor unit performs the vertex manipulation operations and pixel manipulation operations at various degrees of completion based on switching between instructions in the instruction store.