Nano-electrode-array for integrated circuit interconnects

Abstract

An integrated circuit is provided including an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is over the dielectric layer in the trench and via, and a conductor is over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.

1 . An integrated circuit comprising: 
 a dielectric layer having a trench and via provided therein;    a nano-electrode-array over the dielectric layer in the trench and via;    a conductor over the nano-electrode-array; and    the conductor and the nano-electrode-array coplanar with a surface of the dielectric layer.    
   
   
       2 . The integrated circuit as claimed in  claim 1  further comprising: 
 a barrier layer on the dielectric layer in the trench and via; and    the nano-electrode-array on the barrier layer.    
   
   
       3 . The integrated circuit as claimed in  claim 1  further comprising: 
 a self-assembly monolayer on the dielectric layer in the trench and via; and    the nano-electrode-array at least partially embedded in the self-assembly monolayer.    
   
   
       4 . The integrated circuit as claimed in  claim 1  wherein: 
 the nano-electrode-array is on the dielectric layer from which a self-assembly monolayer has been removed.    
   
   
       5 . The integrated circuit as claimed in  claim 1  further comprising: 
 a metallization on the nano-electrode array.    
   
   
       6 . An integrated circuit comprising: 
 an integrated circuit having a trench and via provided in a dielectric layer;    a nano-electrode-array characteristic of activation or electroless deposition over the dielectric layer in the trench and via;    a conductor characteristic of electroless deposition or electroplating over the nano-electrode-array; and    the conductor and the nano-electrode-array planarized by electrochemical, chemical, or chemical-mechanical polishing to be coplanar with a surface of the dielectric layer.    
   
   
       7 . The integrated circuit as claimed in  claim 6  further comprising: 
 a barrier layer on the dielectric layer in the trench and via; and    the nano-electrode-array on the barrier layer; and    the conductor on the nano-electrode-array.    
   
   
       8 . The integrated circuit as claimed in  claim 6  further comprising: 
 a self-assembly monolayer having a radical or tether connection to the dielectric layer in the trench and via;    the dielectric layer being of a porous low dielectric constant material; and    the nano-electrode-array at least partially embedded in the self-assembly monolayer.    
   
   
       9 . The integrated circuit as claimed in  claim 6  further comprising: 
 a self-assembly monolayer having a radical or tether connection to the dielectric layer in the trench and via, the dielectric layer being of a porous low dielectric constant material;    at least one of the radical, the tether connection, or the combination thereof missing from the self-assembly monolayer; and    the nano-electrode-array on the dielectric layer from which the radical, the tether connection, or the combination thereof of the self-assembly monolayer has been removed.    
   
   
       10 . The integrated circuit as claimed in  claim 6  further comprising: 
 a metallization containing a barrier material on the nano-electrode array, the barrier material characterized by electroless deposition.