Method and system for deterministic bist

Abstract

Methods, systems and articles of manufactures are provided for built-in self-testing of high-performance circuits configured to generate and apply test patterns to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test patterns from original test seeds, wherein a response suppression circuit suppresses CUT test responses not generated responsive to a deterministic test pattern of the test pattern plurality prior to compacting a remainder of test pattern responses not suppressed. In one aspect a logic twist counter, a logic shift counter and a logic seed counter are used to generate the test patterns with a seed generation algorithm, determine a subset deterministic test pattern plurality from the original test seeds by looping the original seeds through an input scan register, and suppress responses.

1 . A method for testing circuits, comprising: 
 providing a plurality of original test seeds;    generating a plurality of test patterns from the plurality of original test seeds, the generated test pattern plurality comprising a subset deterministic test pattern plurality;    loading the generated test pattern plurality into a circuit-under-test;    the circuit-under-test producing a plurality of test pattern responses from the generated test pattern plurality, one test pattern response for each of the generated test pattern plurality;    suppressing each of the plurality of test pattern responses not correlated with at least one of the deterministic test pattern plurality subset;    compacting a remainder of the plurality of test pattern responses not suppressed; and    outputting the compacted remainder of test pattern responses to a response monitor.    
   
   
       2 . The method of  claim 1 , further comprising: 
 generating the plurality of test patterns from the plurality of original test seeds through a seed generation algorithm; and    using the seed generation algorithm to identify each of the subset deterministic test pattern plurality.    
   
   
       3 . The method of  claim 2 , further comprising: 
 providing an input scan register configured to load the generated test pattern plurality into the circuit-under-test and a logic structure in communication with the circuit-under-test, the logic structure comprising a twist counter, a shift counter and a seed counter, the seed counter, the shift counter and the twist counter using the seed generation algorithm to generate the plurality of test patterns;    the twist counter and shift counter generating the subset deterministic test pattern plurality from the original test seeds by looping the original seeds through the input scan register.    
   
   
       4 . The method of  claim 3 , wherein the plurality of original test seeds has a quantity value s, the input scan register has a length n, the seed counter is a log 2  s bit seed counter, the shift counter is a log 2  n bit shift counter, and the twist counter is a log 2  2n bit twist counter, further comprising: 
 providing a response suppression logic component for suppressing the plurality of test pattern responses not correlated, the response suppression circuit having a number of inputs x; and    defining the number of inputs x by the formula x=log s+log 2n+log n+1.    
   
   
       5 . The method of  claim 3 , wherein using the seed generation algorithm to generate the plurality of test patterns and identify each of the subset deterministic test pattern plurality comprises: 
 imposing an arbitrary ordering on the deterministic test pattern subset;    choosing a first starting seed for the deterministic test pattern subset;    performing 2n twists on the first starting seed;    if an original test seed on a logic twist cycle is compatible with a deterministic test pattern subset seed, marking a responsively generated test response as covered;    performing a 1-bit shift operation on the original test seeds;    repeating the last five steps of imposing, choosing, performing 2n twists, marking and performing the 1-bit shift operation until n shift operations are carried out;    if there are original test seeds not marked covered, choosing a first unmarked original test seed as a second starting seed and repeating the last six steps of imposing, choosing, performing 2n twists, marking, performing the 1-bit shift operation and repeating with the second starting seed; and    terminating the algorithm when all test seeds are marked covered.    
   
   
       6 . A testing apparatus, comprising: 
 a memory comprising a plurality of original test seeds;    a logic structure in communication with a circuit-under-test and the memory device, the logic structure comprising a seed counter, a twist counter and a shift counter configured to use a seed generation algorithm to produce a plurality of test patterns from the original test seeds;    an input scan register in communication with the logic structure and configured to load the plurality of test patterns into the circuit-under-test; and    a response suppression circuit in communication with the circuit-under-test and the logic structure, the response suppression circuit configured to use the twist counter and the shift counter to: 
 generate a deterministic test pattern subset of the plurality of test patterns by looping the original test seeds through the input scan register, and  
 suppress each of a plurality of test pattern responses generated by the circuit-under-test in response to the generated test pattern plurality not correlated with at least one of the deterministic test pattern plurality subset; and  
 output a remainder of the plurality of test pattern responses not suppressed;  
   a compacter in communication with the response suppression circuit output configured to compress the response suppression circuit output; and    a response monitor configured to receive the compressed response suppression circuit output.    
   
   
       7 . The apparatus of  claim 6 , wherein the logic structure is configured to use a seed generation algorithm to generate the plurality of test patterns from the plurality of original test seeds and identify each of the subset deterministic test pattern plurality.  
   
   
       8 . The apparatus of  claim 7 , wherein the plurality of original test seeds has a quantity value s; 
 the input scan register has a length n;    the seed counter is a log 2  s bit seed counter;    the shift counter is a log 2  n bit shift counter;    the twist counter is a log 2  2n bit twist counter; and    the response suppression circuit further comprises a test mode bit input and a logic component having a number of inputs x defined by the formula x=log s+log 2n+log n+1.    
   
   
       9 . The apparatus of  claim 8 , wherein the response suppression circuit, the space compactor, the circuit-under-test and the logic structure are in circuit communication through a bus structure configured to arbitrate and thereby pass each of the remainder output to the space compactor responsive to response suppression circuit test suppression data.  
   
   
       10 . The apparatus of  claim 9 , wherein the bus structure comprises a plurality of gates and the space compactor is connected to an output of each of the plurality of gates.  
   
   
       11 . The apparatus of  claim 10  wherein the memory is a buffer structure within a scan register or an external ROM.  
   
   
       12 . The apparatus of  claim 11  wherein the response suppression circuit is configured to use the twist counter and the shift counter to generate the deterministic test pattern subset of the plurality of test patterns by looping the original test seeds through the input scan register, and to suppress each of the plurality of test pattern responses not correlated with at least one of the deterministic test pattern plurality subset.  
   
   
       13 . An article of manufacture comprising a computer readable medium having a computer readable program embodied in said medium, wherein the computer readable program, when executed on a computer, causes the computer to generate and apply a test pattern to a circuit-under-test by: 
 generating a plurality of test patterns from a plurality of original test seeds, the generated test pattern plurality comprising a subset deterministic test pattern plurality;    loading the generated test pattern plurality into the circuit-under-test;    suppressing each of a plurality of circuit-under-test test pattern responses not correlated with at least one of the deterministic test pattern plurality subset, the plurality of test pattern responses generated by the circuit-under-test from the generated test pattern plurality;    compacting a remainder of the plurality of test pattern responses not suppressed; and    outputting the compacted remainder of test pattern responses to a response monitor.    
   
   
       14 . The article of manufacture of  claim 13 , wherein the computer readable program, when executed on a computer, further causes the computer to: 
 generate the plurality of test patterns from the plurality of original test seeds through a seed generation algorithm; and    use the seed generation algorithm to identify each of the subset deterministic test pattern plurality.    
   
   
       15 . The article of manufacture of  claim 14 , wherein the computer readable program, when executed on a computer, further causes the computer to: 
 use a logic twist counter, a logic shift counter and a logic seed counter to generate the plurality of test patterns with a seed generation algorithm; and    use the twist counter and shift counter to generate the subset deterministic test pattern plurality from the original test seeds by looping the original seeds through an input scan register.    
   
   
       16 . The article of manufacture of  claim 15  wherein the computer readable program, when executed on a computer, further causes the computer to: 
 execute response suppression logic in suppressing the plurality of test pattern responses not correlated, the response suppression logic having a number of inputs x; and    define the number of inputs x by the formula x=log s+log 2n+log n+1, wherein the plurality of original test seeds has a quantity value s, the input scan register has a length n, the seed counter is a log 2  s bit seed counter, the shift counter is a log 2  n bit shift counter, and the twist counter is a log 2  2n bit twist counter.    
   
   
       17 . The article of manufacture of  claim 16 , wherein the computer readable program, when executed on a computer, further causes the computer to apply the seed generation algorithm to generate the plurality of test patterns and identify each of the subset deterministic test pattern plurality by: 
 imposing an arbitrary ordering on the deterministic test pattern subset;    choosing a first starting seed for the deterministic test pattern subset;    performing 2n twists on the first starting seed;    if an original test seed on a logic twist cycle is compatible with a deterministic test pattern subset seed, marking a responsively generated test response as covered;    performing a 1-bit shift operation on the original test seeds;    repeating the last five steps of imposing, choosing, performing 2n twists, marking and performing the 1-bit shift operation until n shift operations are carried out;    if there are original test seeds not marked covered, choosing a first unmarked original test seed as a second starting seed and repeating the last six steps of imposing, choosing, performing 2n twists, marking, performing the 1-bit shift operation and repeating with the second starting seed; and    terminating the algorithm when all test seeds are marked covered.