Method and system for high frequency clock signal gating

Abstract

A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.

1 . A method, comprising: 
 providing a clock signal having a clock signal amplitude and a clock signal pulse width;    providing a gating signal with a timing relationship to the clock signal;    sending a differential pair current to a buffer differential pair load element;    switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse; and    in response to switching the differential pair current, the buffer differential pair buffering a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.    
   
   
       2 . The method of  claim 2 , wherein switching the differential pair current from the load element to the buffer differential pair is responsive to the gating signal during a first clock signal pulse negative half; 
 further comprising providing normal differential pair current to the buffer differential pair simultaneously with removing the differential pair current from the load element.    
   
   
       3 . The method of  claim 2 , further comprising: 
 presetting a positive buffer differential output and a negative buffer differential output to a differential zero; and    cutting off the positive buffer differential output and negative buffer differential output from the differential zero simultaneously with the steps of switching the differential pair current from the load element to the buffer differential pair and simultaneously providing normal differential pair current to the buffer differential pair.    
   
   
       4 . The method of  claim 3  wherein the clock signal has a frequency of about 2.5 GHz.  
   
   
       5 . A circuit structure, comprising: 
 a clock generator;    a data device having a clock input in communication with the clock generator, a data input and a data output;    a gating device in communication with the data device data input and configured to develop a gating signal with a timing relationship to the clock signal;    a buffer in circuit communication with the data device data output and a clock generator differential clock signal; and    the buffer comprising a differential pair and a current load device;    wherein the data device is configured to provide a gating signal data output to the buffer responsive to a first clock signal pulse; and    wherein, responsive to the first clock signal pulse, the buffer is configured to switch differential pair source current from the current load device to the buffer differential pair and buffer a second immediately subsequent clock signal pulse as a buffered clock signal output, the buffered clock signal output having the clock amplitude and the clock pulse width.    
   
   
       6 . The circuit structure of  claim 5 , wherein the data device is a flip flop having a clock input in inverted circuit communication with the clock generator; and 
 wherein the gating device is a High Speed SerDes (HSS) core comprising logic.    
   
   
       7 . The circuit structure of  claim 6  wherein the buffer comprises a first transistor configured to conduct a highest circuit positive voltage input to a subsequent buffer stage negative output responsive to an inverted gating signal input, and a second transistor configured to conduct a circuit ground potential to a subsequent buffer stage positive output responsive to the inverted gating signal input, the buffer pre-set to provide a zero output; and 
 a subsequent buffer stage clock input in circuit communication with the buffer block stage outputs, a buffer block subsequent buffer stage output pre-set to a differential zero.    
   
   
       8 . The circuit structure of  claim 7 , the buffer further comprising: 
 a third transistor configured to cut off source current to the first transistor and the second transistor responsive to the inverted gating signal input; and    a fourth transistor configured to conduct source current to a current load device responsive to the inverted clock gating signal input.    
   
   
       9 . The circuit structure of  claim 8  wherein the clock signal has a frequency of about 2.5 GHz.