Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices

Abstract

A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.

1 . A voltage divider device, comprising: 
 a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region;    an input voltage coupled between said first and second gates; and    an output voltage taken from at least one of a source of said FET and a drain of said FET;    wherein said output voltage represents a divided voltage with respect to said input voltage.    
   
   
       2 . The device of  claim 1 , wherein said source and drain are coupled to one another.  
   
   
       3 . The device of  claim 1 , wherein said source and drain are of the same polarity type and said body region of said FET is formed with a thickness such that a bias applied to one of said first and second gates is sufficient to invert the entire depth of said channel region of said FET.  
   
   
       4 . The device of  claim 1 , wherein: 
 said first and second gates are formed with equivalent dimensions;    a first gate oxide associated with said first gate is formed at an equivalent thickness as a second gate oxide associated with said second gate;    a work function of said first gate is equivalent to a work function of said second gate, such that said divided output voltage is about half the value of said input voltage; and    said first and second gates comprise a doped semiconductor of the same material as said body.    
   
   
       5 . The device of  claim 1 , wherein said FET is a planar, double gate device with said source and drain formed above said second gate, and said first gate formed above said source and drain.  
   
   
       6 . The device of  claim 1 , wherein said FET comprises a double gate finFET.  
   
   
       7 . The device of  claim 6 , wherein said first and second gates are of opposite polarity types.  
   
   
       8 . The device of  claim 1 , wherein at least one of said first and second gates have selectively variable areas.  
   
   
       9 . The device of  claim 1 , wherein said double gate FET is an asymmetrical device characterized by one or more of: 
 a first gate oxide and a second gate oxide having unequal thicknesses;    said first gate and said second gate having unequal areas; and    said first gate and said second gate having unequal work functions.    
   
   
       10 . A method for implementing an oxide leakage based voltage divider network, the method comprising: 
 coupling an input voltage across first and second gates of a double gate field effect transistor (FET), said first gate and second gates disposed at opposite sides of a body region; and    taking an output voltage from at least one of a source of said FET and a drain of said FET;    wherein said output voltage represents a divided voltage with respect to said input voltage.    
   
   
       11 . The method of  claim 10 , wherein said source and drain are of the same polarity type and said channel region of said FET is formed with thickness such that a bias applied to one of said first and second gates is sufficient to invert the entire depth of said channel region of said FET.  
   
   
       12 . The method of  claim 10 , wherein: 
 said first and second gates are formed with equivalent dimensions;    a first gate oxide associated with said first gate is formed at an equivalent thickness as a second gate oxide associated with said second gate;    a work function of said first gate is equivalent to a work function of said second gate, such that said divided output voltage is about half the value of said input voltage; and    said first and second gates comprise a doped semiconductor of the same material as said body.    
   
   
       13 . The method of  claim 10 , wherein said FET is a planar, double gate device with said source and drain formed above said second gate, and said first gate formed above said source and drain.  
   
   
       14 . The method of  claim 10 , wherein said FET comprises a double gate finFET.