Integrated Circuit with a Transistor Structure Element

Abstract

An integrated semiconductor memory includes at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region, and a region arranged between the first and the second source/drain region. The structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric is arranged on the structure element, and a word line is arranged on the gate dielectric.

1 . An integrated circuit including a memory cell comprising a transistor, the transistor comprising: 
 a structure element containing a semiconductor material, the structure element comprising first and second source/drain regions and a channel region disposed between the first and second source/drain regions, the structure element being insulated from a semiconductor substrate by an insulation layer; and    a wordline disposed adjacent to the channel region, the wordline being insulated from the channel region.    
   
   
       2 . The integrated circuit of  claim 1 , wherein the wordline is insulated from the channel region by a gate dielectric layer.  
   
   
       3 . The integrated circuit of  claim 2 , wherein a portion of the gate dielectric layer has a thickness of less than 3 nm.  
   
   
       4 . The integrated circuit of  claim 2 , wherein a portion of the gate dielectric layer has a thickness which is configured to provide a tunnel contact to the wordline.  
   
   
       5 . The integrated circuit of  claim 1 , wherein the structure element comprises a top side opposed to the insulation layer and side faces adjoining the top side.  
   
   
       6 . The integrated circuit of  claim 5 , wherein the wordline is adjacent to the top side and the side faces.  
   
   
       7 . The integrated circuit of  claim 6 , wherein a thickness of a gate dielectric layer adjoining the top side of the structure element is smaller than a thickness of the gate dielectric layer adjoining the side faces of the structure element.  
   
   
       8 . The integrated circuit of  claim 7 , wherein a difference between the thickness of the gate dielectric adjoining the top side of the structure element and the thickness of the gate dielectric layer adjoining the side faces of the structure element is more than 1 nm.  
   
   
       9 . The integrated circuit of  claim 6 , wherein the thickness of the gate dielectric adjoining the top side of the structure element is less than 3 nm and the thickness of the gate dielectric layer adjoining the side faces of the structure element is more than 4 nm.  
   
   
       10 . The integrated circuit of  claim 1 , further comprising a storage capacitor that is connected with the first source/drain region of the transistor.  
   
   
       11 . The integrated circuit of  claim 10 , wherein the storage capacitor is formed in the semiconductor substrate.  
   
   
       12 . The integrated circuit of  claim 11 , wherein the storage capacitor comprises first and second capacitor electrodes and a capacitor dielectric disposed between the first and second capacitor electrodes.  
   
   
       13 . The integrated circuit of  claim 12 , wherein the capacitor dielectric extends from a bottom of a trench formed in the semiconductor substrate to a bottom surface of the insulation layer.  
   
   
       14 . The integrated circuit of  claim 13 , wherein the capacitor dielectric has a constant thickness.  
   
   
       15 . The integrated circuit of  claim 11 , wherein the wordline is insulated from the channel region by a gate dielectric layer.  
   
   
       16 . The integrated circuit of  claim 15 , wherein a portion of the gate dielectric layer has a thickness of less than 3 nm.  
   
   
       17 . The integrated circuit of  claim 15 , wherein a portion of the gate dielectric layer has a thickness which is configured to provide a tunnel contact to the wordline.  
   
   
       18 . The integrated circuit of  claim 11 , wherein the structure element comprises a top side opposed to the insulation layer and side faces adjoining the top side.  
   
   
       19 . The integrated circuit of  claim 18 , wherein the wordline is adjacent to the top side and the side faces.  
   
   
       20 . The integrated circuit of  claim 19 , wherein a thickness of a gate dielectric adjoining the top side of the structure element is smaller than a thickness of the gate dielectric layer adjoining the side faces of the structure element.