Wafer level package and method of fabricating the same

Abstract

Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

1 . A method of fabricating a wafer level package, the method comprising:
 forming one or more semiconductor chips on a wafer, each semiconductor chip having a connection pad;   patterning a bottom surface of the wafer to form a trench under at least a portion of the connection pad;   patterning a bottom surface of the trench to form a via hole exposing a bottom surface of the connection pad; and   forming a connecting device connected to the connection pad through the via hole.   
   
   
       2 . The method of  claim 1 , wherein the wafer comprises chip regions where the semiconductor chips are disposed and a scribe lane region between the chip regions, and
 wherein the trench is formed under the scribe lane region and edges of the chip regions.   
   
   
       3 . The method of  claim 2 , wherein the trench has a larger width than the scribe lane region. 
   
   
       4 . The method of  claim 2 , wherein the via hole penetrates the wafer under edges of the chip regions, such that the bottom surface of the via hole and the connection pad can be coupled. 
   
   
       5 . The method of  claim 2 , after forming the connecting device, further comprising:
 performing a sawing process to cut the wafer along the scribe lane region to separate each of the semiconductor chips; and   stacking the separated semiconductor chips sequentially on an interconnection substrate,   wherein the stacking of the separated semiconductor chips comprises attaching the connecting device formed on one semiconductor chip to the connection pad formed on another semiconductor chip.   
   
   
       6 . The method of  claim 5 , after stacking the separated semiconductor chips on the interconnection substrate, further comprising:
 injecting a protection layer into a gap between the interconnection substrate and the semiconductor chips to enclose the connecting device.   
   
   
       7 . The method of  claim 5 , wherein the sawing process comprises forming a buffer layer filling the trench, the buffer layer exposing a bottom region of the connecting device. 
   
   
       8 . The method of  claim 1 , wherein the trench is formed by using at least one of a sawing process, and a photolithography and etching process. 
   
   
       9 . The method of  claim 1 , wherein forming the trench comprises:
 patterning a backside of the wafer until the portion of the wafer in the trench has a thickness in a range of about 1 to about 50 micrometers.   
   
   
       10 . The method of  claim 1 , wherein the via hole is formed using at least one of a laser drilling process, and a photolithography and etching process. 
   
   
       11 . The method of  claim 10 , wherein the photolithography and etching process comprises an etch recipe having an etch selectivity between the connection pad and the wafer. 
   
   
       12 . The method of  claim 10 , wherein the laser drilling process comprises:
 forming a preliminary via hole under the connection pad using laser drilling; and   etching the preliminary via hole, thereby forming the via hole.   
   
   
       13 . The method of  claim 1 , before forming the via hole, further comprising performing a backside polishing process to decrease a thickness of the wafer. 
   
   
       14 . The method of  claim 13 , wherein the backside polishing process is performed before forming the trench. 
   
   
       15 . The method of  claim 13 , wherein the backside polishing process is performed after forming the trench. 
   
   
       16 . The method of  claim 13 , wherein the backside polishing process comprises forming a sacrificial layer filling the trench. 
   
   
       17 . The method of  claim 16 , wherein the sacrificial layer has an etch selectivity with respect to the wafer. 
   
   
       18 . The method of  claim 13 , wherein the backside polishing process comprises forming a supporting layer on the wafer. 
   
   
       19 . The method of  claim 18 , wherein the supporting layer is removable by exposure to one or more of heat and ultraviolet radiation. 
   
   
       20 . The method of  claim 18 , wherein the supporting layer has substantially the same thermal expansion coefficient as the wafer. 
   
   
       21 . The method of  claim 1 , wherein forming the connecting device comprises:
 forming a connecting plug which fills the via hole and is connected to the connection pad; and   forming a bump connected to the connection pad through the connecting plug.   
   
   
       22 . The method of  claim 21 , wherein forming the connecting device further comprises:
 forming an under-bump metallization (UBM) pattern before forming the connecting plugs, the UBM pattern covering the bottom surface of the connection pad exposed through the via hole.   
   
   
       23 . The method of  claim 21 , wherein forming the connecting device further comprises at least one of an electroplating process, a solder jet process, a screen printing process, and a Controlled Collapse Chip Connection New Process (C4NP). 
   
   
       24 . The method of  claim 23 , wherein the connection pad are a seed layer for the electroplating process when the electroplating process is used to form the connecting device. 
   
   
       25 . The method of  claim 1 , wherein forming each of the semiconductor chips comprises:
 forming an internal circuit comprising microelectronic devices on the wafer;   forming an interconnection structure connecting the microelectronic devices with each other;   forming an input/output pad connected to the internal circuit through the interconnection structure; and   forming a redistribution structure connected to the input/output pad,   wherein the redistribution structure comprises the connection pad which is disposed on the via hole and electrically connects the connecting device to the input/output pad.   
   
   
       26 . A wafer level package, comprising:
 an interconnection substrate; and   one or more semiconductor chips stacked on the interconnection substrate, wherein at least one of the semiconductor chips comprises:
 a central region for an internal circuit and a connection region disposed adjacent to the central region; 
 a redistribution structure connected to the internal circuit on the semiconductor chip, the redistribution structure comprising a connection pad disposed on the connection region; and 
 a connecting device in the connection region, the connecting device penetrating through the semiconductor chip and connected to the connection pad, 
 wherein the thickness of the connection region is smaller than the thickness of the central region. 
   
   
   
       27 . The wafer level package of  claim 26 , wherein the at least one of the semiconductor chips further comprises a semiconductor substrate, the internal circuit disposed on the semiconductor substrate, an interconnection structure connected to the internal circuit, and an input/output pad connected to the interconnection structure,
 wherein the connecting device comprises a connection plug penetrating the semiconductor chip and a bump disposed under the connection region to be connected to the connection plug.   
   
   
       28 . The wafer level package of  claim 27 , wherein the thickness of the bump is larger than the difference in thickness between the central region and the connection region. 
   
   
       29 . The wafer level package of  claim 27 , further comprising:
 an under-bump metallization (UBM) layer interposed between the connection plug and the connection pad.   
   
   
       30 . The wafer level package of  claim 29 , wherein the UBM layer comprises one or more of nickel (Ni), chrome (Cr), copper (Cu), tungsten titanium (TiW) and gold (Au). 
   
   
       31 . The wafer level package of  claim 27 , wherein the semiconductor chips are electrically connected to each other through the bump of a semiconductor chip and the connection pad of another semiconductor chip. 
   
   
       32 . The wafer level package of  claim 31  further comprising:
 a protection layer disposed between the semiconductor chips, the protection layer enclosing the bump.   
   
   
       33 . The wafer level package of  claim 27 , wherein the bump of the at least one of semiconductor chips contacts a connection terminal on the interconnection substrate, thereby electrically connecting the at least one of semiconductor chips to the interconnection substrate. 
   
   
       34 . The wafer level package of  claim 33 , further comprising a protection layer disposed between the at least one of semiconductor chips and the interconnection substrate, the protection layer enclosing the bump.