Symmetrical MIMCAP capacitor design

Abstract

Semiconductor chip capacitance circuits and methods are provided comprising at least two capacitors mounted close to a substrate, wherein each capacitor has a lateral lower conductive plate mounted near enough to the substrate to have extrinsic capacitance greater than an upper plate extrinsic capacitance. One half of lower plates and one half of upper plates are connected to a first port, and a remaining one half of upper plates and lower plates are connected to a second port, the first and second port having about equal extrinsic capacitance from the lower plates. In one aspect, the substrate comprises a front-end-of-line capacitor defining a substrate footprint, and the at least two capacitors are back-end-of-line Metal-Insulator-Metal Capacitors disposed above the footprint. In another aspect, the at least two capacitors are at least four capacitors arrayed in a rectangular array generally parallel to the substrate.

1 . A capacitance circuit assembly mounted on a semiconductor chip comprising: 
 a chip substrate;    at least two capacitors mounted close to the substrate;    wherein each capacitor has first and second conductive plates separated by a dielectric material;    wherein each second conductive plate is mounted flat near enough to said substrate to have a second plate extrinsic capacitance with said substrate greater than an extrinsic capacitance of each first conductive plate;    one half of said first plates and one half of said second plates connected to a first port by a first port circuitry, wherein the first port has a first port composite extrinsic capacitance from the one half of said second plates; and    a remaining one half of said first plates and a remaining one half of said second plates connected to a second port by a second port circuitry, wherein the second port has a second port composite extrinsic capacitance from the remaining one half of said second plates, the second port composite extrinsic capacitance about equal to the first port composite extrinsic capacitance.    
   
   
       2 . The structure of  claim 1  wherein the at least two capacitors are Metal-Insulator-Metal Capacitors, and the capacitance circuit assembly is located in a back-end-of-line semiconductor capacitor circuit.  
   
   
       3 . The structure of  claim 2 , wherein the substrate further comprises a front-end-of-line capacitor with first and second terminals, the front-end-of-line capacitor defining a substrate footprint; 
 wherein the first port is electrically connected to the front-end-of-line capacitor structure first terminal and the second port is electrically connected to the front-end-of-line capacitor structure second terminal; and    wherein the at least two capacitors are disposed above the substrate within the front-end-of-line capacitor footprint.    
   
   
       4 . The structure of  claim 3  wherein the at least two capacitors are at least four capacitors.  
   
   
       5 . The structure of  claim 4  wherein the at least four capacitors are arrayed in a rectangular array generally parallel to the substrate.  
   
   
       6 . The structure of  claim 3 , further comprising a Vertical Native Capacitor disposed above the substrate within the front-end-of-line capacitor footprint and having first and second terminals, and wherein the first port is electrically connected to the Vertical Native Capacitor first terminal and the second port is electrically connected to the Vertical Native Capacitor second terminal.  
   
   
       7 . The structure of  claim 1  wherein each of the first and second plates are formed of the same material.  
   
   
       8 . The structure of  claim 7  wherein the plates are a metal or polysilicon.  
   
   
       9 . The structure of  claim 7  wherein the dielectric material has a permeability value greater than about 4 (er >4).  
   
   
       10 . A method for forming a semiconductor chip capacitance circuit, comprising the steps of: 
 forming a front end of line substrate structure;    mounting at least two capacitors close to the substrate, wherein each capacitor has first and second conductive plates separated by a dielectric material, and wherein each second conductive plate is mounted flat near enough to said substrate to have a second plate extrinsic capacitance with said substrate greater than an extrinsic capacitance of each first conductive plate;    connecting one half of said first plates and one half of said second plates to a first port by a first port circuitry, wherein the first port has a first port composite extrinsic capacitance from the one half of said second plates; and    connecting a remaining one half of said first plates and a remaining one half of said second plates to a second port by a second port circuitry, wherein the second port has a second port composite extrinsic capacitance from the remaining one half of said second plates, the second port composite extrinsic capacitance about equal to the first port composite extrinsic capacitance.    
   
   
       11 . The method of  claim 10  wherein the at least two capacitors are Metal-Insulator-Metal Capacitors, further comprising the step of locating the at least two capacitors in a back-end-of-line semiconductor capacitor circuit.  
   
   
       12 . The method of  claim 11 , further comprising the steps of: 
 providing a front-end-of-line capacitor with first and second terminals in the substrate;    the front-end-of-line capacitor defining a substrate footprint;    connecting the first port electrically to the front-end-of-line capacitor structure first terminal;    connecting the second port electrically to the front-end-of-line capacitor structure second terminal; and    disposing the at least two capacitors above the substrate within the front-end-of-line capacitor footprint.    
   
   
       13 . The method of  claim 12  wherein the at least two capacitors are at least four capacitors.  
   
   
       14 . The method of  claim 13 , further comprising the step of disposing the at least four capacitors in a rectangular array generally parallel to the substrate.  
   
   
       15 . The method of  claim 12 , further comprising the steps of: 
 disposing a Vertical Native Capacitor above the substrate within the front-end-of-line capacitor footprint, the Vertical Native Capacitor having first and second terminals;    connecting the first port electrically to the Vertical Native Capacitor first terminal; and    connecting the second port electrically to the Vertical Native Capacitor second terminal.    
   
   
       16 . The method of  claim 10  wherein each of the first and second plates are formed of the same material.  
   
   
       17 . The method of  claim 16  wherein the plates are a metal or polysilicon.  
   
   
       18 . The method of  claim 16  wherein the dielectric material has a permeability value greater than about 4 (er >4).  
   
   
       19 . A semiconductor circuit structure comprising: 
 a chip substrate comprising a front-end-of-line metal oxide silicon capacitor with first and second terminals, the metal oxide silicon capacitor defining a front-end-of-line capacitor footprint;    at least two back-end-of-line Metal-Insulator-Metal Capacitors electrically connected to the front-end-of-line capacitor structure and mounted close to the substrate and above the front-end-of-line capacitor footprint, wherein Metal-Insulator-Metal bottom conductive plates are mounted flat near enough to said substrate to have a bottom plate extrinsic capacitances with said substrate greater than Metal-Insulator-Metal top conductive plate extrinsic capacitances;    one half of said top plates and one half of said bottom plates connected to a first port by a first port circuitry, wherein the first port has a first port composite extrinsic capacitance from the one half of said bottom plates; and    a remaining one half of said top plates and a remaining one half of said bottom plates connected to a second port by a second port circuitry, wherein the second port has a second port composite extrinsic capacitance from the remaining one half of said bottom plates, the second port composite extrinsic capacitance about equal to the first port composite extrinsic capacitance.