Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package

Abstract

In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are formed on the top surface of the body to connect to an external terminal. A shielding conductive film is formed on the surfaces excluding the top surface of the body where the pattern is formed. A conductive via is extended through the body to connect one of the electrode pads with the conductive film.

1 . A semiconductor chip comprising:
 a body having a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces;   a plurality of electrode pads formed on the top surface of the body to connect to an external terminal;   a shielding conductive film formed on the surfaces excluding the top surface of the body where the pattern is formed; and   a conductive via extending through the body to connect one of the electrode pads with the conductive film.   
   
   
       2 . A semiconductor chip according to  claim 1 , wherein the electrode pad connected to the conductive via is grounded. 
   
   
       3 . A semiconductor chip according to  claim 1 , wherein the conductive film is formed only on the underside surface of the body. 
   
   
       4 . A semiconductor chip package comprising:
 a semiconductor chip including:
 a body having a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces; 
 a plurality of electrode pads formed on the top surface of the body to connect to an external terminal; 
 a shielding conductive film formed on the surfaces excluding the top surface of the body where the pattern is formed; and 
 a conductive via extending through the body to connect one of the electrode pads with the conductive film, 
   a substrate where a ground lead pattern and a plurality of lead patterns are formed; and   a plurality of bumps disposed between the respective electrode pads of the semiconductor chip and the respective lead patterns of the substrate to electrically connect the semiconductor chip with the substrate.   
   
   
       5 . The semiconductor chip package according to  claim 4 , wherein the electrode pad connected to the via hole is connected to the ground lead pattern of the substrate. 
   
   
       6 . The semiconductor chip package according to  claim 4 , wherein the conductive film is formed only on the underside surface of the semiconductor chip. 
   
   
       7 . A method for manufacturing a semiconductor chip comprising:
 forming via holes in a wafer including unit chip areas to connect from an electrode pad on a top surface of a wafer where a pattern is formed to an underside surface of the wafer opposing the top surface so that at least one of the via holes is formed in each of the unit chip areas;   filling the via hole with conductive material;   forming a conductive film on the underside surface of the wafer to contact the conductive material filled in the via hole; and   cutting the wafer into unit chips.   
   
   
       8 . The method according to  claim 7 , further comprising:
 forming a shielding conductive material on a side surface of the cut semiconductor chip.