Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device contains a CMOS circuit that includes a plurality of N-channel transistors and a plurality of P-channel transistors. The plurality of N-channel transistors is provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure. The plurality of P-channel transistors are provided with device isolation by the other of the gate isolation structure and the shallow trench isolation structure.

1 . A semiconductor integrated circuit device comprising a CMOS circuit that includes
 a plurality of N-channel transistors provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure, and   a plurality of P-channel transistors provided with device isolation by the other of the gate isolation structure and the shallow trench isolation structure.   
   
   
       2 . The semiconductor integrated circuit device according to  claim 1 , further comprising:
 a P-well region in which the plurality of N-channel transistors are formed; and   an N-well region in which the plurality of P-channel transistors are formed.   
   
   
       3 . The semiconductor integrated circuit device according to  claim 1 , wherein the plurality of N-channel transistors are provided with device isolation by the gate isolation structure, and the plurality of P-channel transistors are provided with device isolation by the shallow trench isolation structure. 
   
   
       4 . The semiconductor integrated circuit device according to  claim 1 , wherein the gate isolation structure includes a dummy gate electrode. 
   
   
       5 . The semiconductor integrated circuit device according to  claim 1 , wherein the CMOS circuit includes a plurality of basic cells that form a standard cell. 
   
   
       6 . The semiconductor integrated circuit device according to  claim 1 , wherein the CMOS circuit includes a plurality of basic cells that form a gate array. 
   
   
       7 . The semiconductor integrated circuit device according to  claim 1 , wherein the plurality of N-channel transistors have the same channel width as each other, and the plurality of P-channel transistors have the same channel width as each other. 
   
   
       8 . The semiconductor integrated circuit device according to  claim 1 , wherein the plurality of N-channel transistors include a plurality of first N-channel transistors having a first channel width and a plurality of second N-channel transistors having a second channel width different from the first channel width, and
 the plurality of P-channel transistors include a plurality of first P-channel transistors having a third channel width and a plurality of second P-channel transistors having a fourth channel width different from the third channel width.   
   
   
       9 . A semiconductor integrated circuit device comprising a delay circuit that includes
 a plurality of P-channel transistors provided with device isolation by a gate isolation structure, and   a plurality of N-channel transistors provided with device isolation by a shallow trench isolation structure.   
   
   
       10 . The semiconductor integrated circuit device according to  claim 9 , wherein the gate isolation structure includes a dummy gate electrode. 
   
   
       11 . The semiconductor integrated circuit device according to  claim 9 , further comprising:
 an N-well region in which the plurality of P-channel transistors are formed; and   a P-well region in which the plurality of N-channel transistors are formed.   
   
   
       12 . A semiconductor integrated circuit device comprising:
 a first region that includes a plurality of first channel transistors provided with device isolation by a shallow trench isolation structure; and   a second region that includes a plurality of second channel transistors provided with device isolation by a gate isolation structure.   
   
   
       13 . The semiconductor integrated circuit device according to  claim 12 , further comprising:
 a first-well region in which the plurality of first channel transistors is formed; and   a second-well region in which the plurality of second channel transistors is formed.   
   
   
       14 . The semiconductor integrated circuit device according to  claim 12 , wherein the first channel transistors are N-channel transistors, and the second channel transistors are P-channel transistors. 
   
   
       15 . The semiconductor integrated circuit device according to  claim 12 , wherein the first channel transistors are P-channel transistors, and the second channel transistors are N-channel transistors. 
   
   
       16 . The semiconductor integrated circuit device according to  claim 12 , wherein the gate isolation structure includes a dummy gate electrode. 
   
   
       17 . The semiconductor integrated circuit device according to  claim 12 , wherein the plurality of first channel transistors and the plurality of second channel transistors form a plurality of basic cells of a standard cell. 
   
   
       18 . The semiconductor integrated circuit device according to  claim 12 , wherein the plurality of first channel transistors and the plurality of second channel transistors form a plurality of basic cells of a gate array. 
   
   
       19 . The semiconductor integrated circuit device according to  claim 12 , wherein the plurality of first channel transistors have the same channel width as each other, and the plurality of second channel transistors have the same channel width as each other. 
   
   
       20 . The semiconductor integrated circuit device according to  claim 12 , wherein the plurality of first channel transistors include a plurality of first transistors having a first channel width and a plurality of second transistors having a second channel width different from the first channel width, and
 the plurality of second channel transistors include a plurality of third transistors having a third channel width and a plurality of fourth transistors having a fourth channel width different from the third channel width.