Method of manufacturing semiconductor device

Abstract

A method of manufacturing semiconductor devices includes forming a trench in a predetermined region of a substrate. A first insulating layer and a second insulating layer are formed on a entire surface so that the trench is gap-filled. The first and second insulating layers are polished until a top surface of the substrate is exposed. A wet etch process of a low selectivity is performed, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. A third insulating layer is formed on the entire surface, so that the trench is gap-filled, thereby forming an isolation structure.

1 . A method of manufacturing a semiconductor device, comprising the steps of:
 forming a trench in a predetermined region of a semiconductor substrate;   providing a first insulating layer within the trench to at least partly fill the trench and over the semiconductor substrate, the first insulating layer having an over-hang at an opening of the trench;   providing a second insulating layer within the trench and over the first insulating layer;   removing the second insulating layer and the over-hang of the first insulating layer; and   providing a third insulating layer within the trench over the first insulating layer to form an isolation structure.   The method of  claim 1 , wherein a hard mask is provided over the substrate and defining the opening of the trench, the method further comprising:   
   
   
       2 . The method of  claim 1 , polishing the first and second insulating layers until the hard mask is exposed prior to removing the second insulating layer and the over-hang. 
   
   
       3 . The method of  claim 1 , wherein the removing step involves a wet etch process. 
   
   
       4 . The method of  claim 3 , wherein the wet etch process involves a low selectivity process, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. 
   
   
       5 . The method of  claim 4 , wherein an etch selectivity of the second insulating layer to the first insulating layer is no more than 8:1. 
   
   
       6 . The method of  claim 5 , wherein the etch selectivity is at least 2:1. 
   
   
       7 . The method of  claim 1 , wherein the second insulating layer is substantially removed from the trench. 
   
   
       8 . The method of  claim 7 , wherein the second insulating layer is stripped from the trench. 
   
   
       9 . The method of  claim 1 , wherein the first and third insulating layers are formed of a HDP oxide layer. 
   
   
       10 . The method of  claim 1 , wherein the second insulating layer is formed of SOG, BPSG or O 3 -TEOS. 
   
   
       11 . The method of  claim 1 , wherein the first and third insulating layers are of the same kind, and the second insulating layer is of a different kind. 
   
   
       12 . The method of  claim 1 , wherein the removing step involves a dry etch process. 
   
   
       13 . The method of  claim 12 , wherein the wet etch process involves a low selectivity process, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. 
   
   
       14 . The method of  claim 13 , wherein an etch selectivity of the second insulating layer to the first insulating layer is no more than 8:1. 
   
   
       15 . The method of  claim 14 , wherein the etch selectivity is at least 2:1.