US2007263472A1PendingUtilityA1

Process environment variation evaluation

49
Individually held — no corporate assignee on recordPriority: May 11, 2006Filed: May 11, 2006Published: Nov 15, 2007
Est. expiryMay 11, 2026(expired)· nominal 20-yr term from priority
Inventors:Brent A. AndersonEdward J. NowakNoah Zamdmer
H10P 74/277
49
PatentIndex Score
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Claims

Abstract

Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Claims

exact text as granted — not AI-modified
1 . A structure comprising: 
 a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in a vicinity of the plurality of electrical structures.    
   
   
       2 . The structure of  claim 1 , wherein the plurality of electrical structures includes one of a plurality of resistors, a plurality of diodes, a plurality of ring oscillators and a plurality of transistors.  
   
   
       3 . The structure of  claim 1 , wherein each of the plurality of electrical structures includes: 
 a first polarity field effect transistor (FET) and a second polarity FET, and    wherein gates and drains of the first polarity FET and the second polarity FET are coupled to a first pad and sources of the first polarity FET and the second polarity FET are coupled to a second pad.    
   
   
       4 . The structure of  claim 3 , wherein each of the plurality of structures measures a threshold voltage.  
   
   
       5 . The structure of  claim 1 , wherein each of the plurality of electrical structures includes: 
 a first polarity field effect transistor (FET) and a second polarity FET, and    wherein a source of the first polarity FET is coupled to a first pad, a gate and a drain of the first polarity FET are coupled to a source of the second polarity FET, and a gate and a drain of the second polarity FET are coupled to a second pad.    
   
   
       6 . The structure of  claim 5 , wherein a body of the first polarity FET is coupled to the source of the first polarity FET and a body of the second polarity FET is coupled to the source of the second polarity FET.  
   
   
       7 . The structure of  claim 5 , wherein each of the plurality of structures measures an off current (I off ).  
   
   
       8 . The structure of  claim 1 , wherein the process environment variation includes one of: a spacer etch variation, a photolithography exposure variation, a gate length variation, a variation in film deposition, and an anneal temperature gradient.  
   
   
       9 . The structure of  claim 1 , wherein the non-collinear fashion includes a substantially triangulated fashion.  
   
   
       10 . The structure of  claim 1 , wherein the plurality of electrical structures are substantially identical.  
   
   
       11 . A structure comprising: 
 a first polarity field effect transistor (FET) coupled to a second polarity FET, each of the first polarity FET and the second polarity FET coupled to a first pad and a second pad; and    wherein the structure provides for independent measurement of the first polarity FET and the second polarity FET using only the first pad and the second pad.    
   
   
       12 . The structure of  claim 11 , wherein gates and drains of the first polarity FET and the second polarity FET are coupled to the first pad and sources of the first polarity FET and second polarity FET are coupled to the second pad.  
   
   
       13 . The structure of  claim 11 , wherein a source of the first polarity FET is coupled to a first pad, a gate and a drain of the first polarity FET are coupled to a source of the second polarity FET, and a gate and a drain of the second polarity FET are coupled to the second pad.  
   
   
       14 . The structure of  claim 13 , wherein a body of the first polarity FET is coupled to the source of the first polarity FET and a body of the second polarity FET is coupled to the source of the second polarity FET.  
   
   
       15 . A method of determining a gradient field of a process environment variation, the method comprising: 
 providing a plurality of electrical structures arranged in a non-collinear fashion in a substrate;    performing a process on the substrate;    measuring an electrical property of each of the electrical structures; and    determining a magnitude and a direction of the process environment variation in the vicinity of the plurality of electrical structures based on the measurements.    
   
   
       16 . The method of  claim 15 , wherein the plurality of electrical structures includes one of a plurality of resistors, a plurality of diodes, a plurality of ring oscillators and a plurality of transistors.  
   
   
       17 . The method of  claim 15 , wherein the providing includes providing each of the plurality of electrical structures as: 
 a first polarity field effect transistor (FET) and a second polarity FET,    wherein gates and drains of the first polarity FET and the second polarity FET are coupled to a first pad and sources of the first polarity FET and the second polarity FET are coupled to a second pad.    
   
   
       18 . The method of  claim 17 , wherein the electrical property includes a threshold voltage.  
   
   
       19 . The method of  claim 15 , wherein the providing includes providing each of the plurality of electrical structures as: 
 a first polarity field effect transistor (FET) and a second polarity FET,    wherein a source of the first polarity FET is coupled to a first pad, a gate and a drain of the first polarity FET are coupled to a source of the second polarity FET, and a gate and a drain of the second polarity FET are coupled to a second pad.    
   
   
       20 . The method of  claim 19 , wherein the electrical property includes an off current (I off ).  
   
   
       21 . The method of  claim 15 , wherein the process environment variation includes one of: a spacer etch variation, a photolithography exposure variation, a gate length variation, a variation in film deposition, and an anneal temperature gradient.  
   
   
       22 . The method of  claim 15 , wherein the providing includes providing the plurality of electrical structures in a substantially triangulated fashion.  
   
   
       23 . The method of  claim 15 , wherein the providing includes providing the plurality of electrical structures interconnected to a plurality of pads.  
   
   
       24 . A method of independently evaluating transistors, the method comprising: 
 forming a first polarity field effect transistor (FET) coupled to a second polarity FET, each of the first polarity FET and the second polarity FET coupled to a first pad and a second pad; and    independently measuring the first polarity FET and the second polarity FET using only the first pad and the second pad.    
   
   
       25 . The method of  claim 24 , wherein the forming includes forming gates and drains of the first polarity FET and the second polarity FET are coupled to the first pad and sources of the first polarity FET and second polarity FET are coupled to the second pad.  
   
   
       26 . The method of  claim 25 , wherein the measuring includes measuring a threshold voltage.  
   
   
       27 . The method of  claim 24 , wherein the forming includes coupling a source of the first polarity FET to a first pad, a gate and a drain of the first polarity FET to a source of the second polarity FET, and a gate and a drain of the second polarity FET to the second pad.  
   
   
       28 . The method of  claim 27 , wherein the forming further includes coupling a body of the first polarity FET to the source of the first polarity FET and a body of the second polarity FET to the source of the second polarity FET.  
   
   
       29 . The method of  claim 27 , wherein the measuring includes measuring an off-current (Ioff).  
   
   
       30 . The method of  claim 24 , wherein the measuring includes at least one of: 
 applying a positive voltage ramp to the first pad with respect to the second pad to maintain the first polarity FET in an off-state and measuring the second polarity FET; and    applying a negative voltage ramp to the first pad with respect to the second pad to maintain the second polarity FET in an off-state and measuring the first polarity FET.

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