Driver circuit

Abstract

A driver circuit for driving a load ( 3 ) connected between an output (FO) of a first channel driver (D 1 ) and an output (RO) of a second channel driver (D 2 ). The first and second channel drivers (D 1 , D 2 ) each include switch transistors for charging and discharging the gates of upper and lower output transistors in response to a command from an input pulse, a charging/discharging circuit (A 2, B 2 ) for determining a charging/discharging speed, and a detector circuit (A 1 , B 1 ) for detecting a state of the channel driver on the opposite side. A dead time period and a speed of charging/discharging the gates of the upper and lower output transistors are changed according to the state of the channel driver on the opposite side. Thus, it is possible to achieve a channel driver circuit which can prevent a shoot-through current, adjust an output slew rate, and obtain preferred linearity as an input-output characteristic.

1 .- 8 . (canceled)  
   
   
       9 . A driver circuit, in which a linear input channel driver comprises: 
 a converter circuit for converting, into a current, a voltage difference between output voltages of an output of a first channel driver and an output of a second channel driver;    a capacitance charged by an output of the converter circuit;    an error amplifier for comparing a voltage difference between a linear input voltage and an output voltage of the capacitance with a reference voltage;    a comparator circuit for comparing a triangular wave and an output voltage of the error amplifier to generate a PWM pulse;    a charging/discharging circuit for charging and discharging gates of upper and lower output transistors on the outputs of the first and second channel drivers, according to a level of an output of the amplifier circuit and the linear input; and    a comparator for comparing the linear input and the reference voltage, wherein    a change is made to a dead time period and a speed of charging/discharging the gates of the upper and lower output transistors, according to an output of the comparator.    
   
   
       10 . The driver circuit according to  claim 9 , wherein 
 when the output of the comparator is set at “H”, dead time is provided at a falling edge of one input, the gate of one of the lower output transistors is discharged at a higher speed, the gate of one of the upper output transistors is discharged at a lower speed, the dead time is provided at a rising edge of an input on an opposite side, the gate of the upper output transistor on the opposite side is discharged at a higher speed, and the gate of the lower output transistor on the opposite side is discharged at a lower speed, and    when the output of the comparator is set at “L”, dead time is provided at the rising edge of one input, the gate of one of the lower output transistors is discharged at a lower speed, the gate of one of the upper output transistors is discharged at a higher speed, the dead time is provided at the falling edge of the input (output) on the opposite side, the gate of the upper output transistor on the opposite side is discharged at a lower speed, and the gate of the lower output transistor on the opposite side is discharged at a higher speed.    
   
   
       11 . The driver circuit according to  claim 10 , wherein the comparator is replaced with a window comparator, and when the linear input is close to the reference voltage, no dead time is provided for a driving pulse for charging and discharging the output transistors on both sides, and the gates of the upper and lower transistors are discharged at a higher speed.  
   
   
       12 . The driver circuit according to  claim 9 , further comprising an amplifier having bipolar outputs as the error amplifier, and first and second comparator circuits as the comparator circuits, wherein 
 a comparison is made between a positive output of the amplifier and the triangular wave by the first comparator circuit to generate a first PWM pulse, a comparison is made between a negative output of the amplifier and the triangular wave by the second comparator circuit to generate a second PWM pulse,    an output of the first comparator is supplied as one input pulse to a timing pulse generator of the first channel driver,    an output of the second comparator is supplied as the other input pulse to a timing pulse generator of the second channel driver,    the output of the second comparator is supplied to a timing pulse generator of the first channel driver as information about a state of the second channel driver to change a dead time period and a speed of charging/discharging the gates of the upper and lower output transistors of the first channel driver, and    the output of the first comparator is supplied to the timing pulse generator of the second channel driver as information about a state of the first channel driver to change a dead time period and a speed of charging/discharging the gates of the upper and lower output transistors of the second channel driver.