Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

1 . A semiconductor device having a MOS gate side surface structure, comprising: 
 a semiconductor substrate of one conductivity type;    a trench selectively formed into the semiconductor substrate;    a polycrystalline semiconductor gate electrode region filling the trench;    a substrate insulator film between the trench and the polycrystalline semiconductor gate electrode region;    a gate insulator film covering the surface of the polycrystalline semiconductor gate electrode region;    a deposited semiconductor layer in contact with the gate insulator film in a region on the trench and in contact with the surface of the semiconductor substrate in a region other than the region on the trench, the deposited semiconductor layer having a buffer region of the one conductivity type in contact with the surface of the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the gate insulator film on the side opposite to the buffer region;    an interlayer insulator film covering the buffer region; and    an emitter electrode covering the interlayer insulator film, and in contact with both the base region and the emitter region on the side opposite to the side in contact with the gate insulator film.    
   
   
       2 . The semiconductor device as claimed in  claim 1 , wherein the buffer region has an impurity concentration higher than that of the semiconductor substrate.  
   
   
       3 . The semiconductor device as claimed in  claim 1 , wherein the deposited semiconductor layer is a single crystal or polycrystalline semiconductor layer of the one conductivity type.  
   
   
       4 . The semiconductor device as claimed in  claim 1 , wherein the trench has a side wall forming an angle of 90° or less with the surface of the semiconductor substrate.  
   
   
       5 . A semiconductor device having a MOS gate side surface structure, comprising: 
 a semiconductor substrate of one conductivity type;    a substrate insulator film selectively formed on the surface of the semiconductor substrate;    a deposited semiconductor layer formed on the surface of the semiconductor substrate and the substrate insulator film, the deposited semiconductor layer having a buffer region of the one conductivity type in contact with the surface of the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the substrate insulator film, and an emitter region of the one conductivity type in the base region, the emitter region being at a position holding the surface of the base region between the buffer region and the emitter region;    a gate electrode of polycrystalline semiconductor on the surface of the buffer region and on the surface of the base region held between the buffer region and the emitter region;    a gate insulator film held between the gate electrode and the buffer region, and between the gate electrode and the base region;    an interlayer insulator film covering the gate electrode of the polycrystalline semiconductor; and    an emitter electrode in contact with both the base region and the emitter region.    
   
   
       6 . The semiconductor device as claimed in  claim 5 , wherein the buffer region has an impurity concentration higher than that of the semiconductor substrate.  
   
   
       7 . The semiconductor device as claimed in  claim 5 , wherein the deposited semiconductor layer is a single crystal or polycrystalline semiconductor layer of the one conductivity type.