Flat panel display and fabrication method and thereof

Abstract

The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel.

1 . A method for fabricating a flat panel display, the flat panel display comprising a plurality of sub-pixels, the method comprising: 
 providing a substrate;    forming an amorphous silicon layer on the substrate;    performing a first crystallization process to re-crystallize the amorphous silicon layer so that the amorphous silicon layer becomes a polysilicon layer;    forming a patterned absorbing layer to cover an active area pattern of a driving thin film transistor (TFT) in each of the sub-pixels and to expose portions of the polysilicon layer;    performing a second crystallization process to re-crystallize the exposed portions of the polysilicon layer so that the grain structure of the exposed portions of the polysilicon layer is different from the grain structure of a plurality of active areas covered by the active area patterns of the driving TFTs;    removing the patterned absorbing layer; and    removing portions of the polysilicon layer to form the active area of the driving TFT and to form an active area of a switching TFT in the exposed portions of the polysilicon layer of each sub-pixel;    wherein each of the active areas comprises a channel region, a source region, and a drain region.    
   
   
       2 . The method as claimed in  claim 1 , wherein the method further comprises: 
 forming a gate insulating layer and a metal layer on the substrate sequentially; and    removing portions of the metal layer to form a plurality of gates of the switching TFTs and the driving TFTs.    
   
   
       3 . The method as claimed in  claim 1 , wherein the flat panel display comprises a periphery circuit area, and the step of removing portions of the polysilicon layer further comprises forming at least an active area of a peripheral driving TFT in the periphery circuit area.  
   
   
       4 . The method as claimed in  claim 3 , wherein the grain structure of a channel region of the peripheral driving TFT in the periphery circuit area is the same as the grain structure of the channel region of the switching TFT in each of the sub-pixels.  
   
   
       5 . The method as claimed in  claim 1 , wherein the first crystallization process comprises a solid-phase crystallization (SPC) process.  
   
   
       6 . The method as claimed in  claim 5 , wherein the SPC process comprises a furnace annealing process, a rapid thermal process (RTP), or an alternating magnetic field crystallization (AMFC) process.  
   
   
       7 . The method as claimed in  claim 1 , wherein the second crystallization process comprises an excimer laser annealing (ELA) process.  
   
   
       8 . The method as claimed in  claim 7 , wherein the ELA process comprises a solid-state laser (SSL) or an excimer laser processes.  
   
   
       9 . The method as claimed in  claim 1 , wherein the grain structure of the channel regions of the driving TFTs comprises a dendrite grain structure, and the grain structure of the channel regions of the switching TFTs comprises a columnar grain structure.  
   
   
       10 . The method as claimed in  claim 1 , wherein the standard deviation of the carrier mobility in the channel regions of the driving TFTs is smaller than the standard deviation of the carrier mobility in the channel regions of the switching TFTs.  
   
   
       11 . A flat panel display comprising: 
 a pixel array area comprising a plurality of sub-pixels, each of the sub-pixels comprising a first TFT that comprises a channel region with a first grain structure; and    a periphery circuit area comprising at least a peripheral driving TFT that comprises a channel region with a second grain structure, the second grain structure being different from the first grain structure.    
   
   
       12 . The flat panel display as claimed in  claim 11 , wherein the first grain structure comprises a dendrite grain structure, and the second grain structure comprises a columnar grain structure.  
   
   
       13 . The flat panel display as claimed in  claim 11 , wherein the first TFT is a driving TFT of each of the sub-pixels.  
   
   
       14 . The flat panel display as claimed in  claim 11 , wherein the flat panel display further comprises a second TFT in each of the sub-pixels, the grain structure of a channel region of the second TFT being different from the first grain structure.  
   
   
       15 . The flat panel display as claimed in  claim 14 , wherein the second TFTs are switching TFTs of the sub-pixels.  
   
   
       16 . The flat panel display as claimed in  claim 14 , wherein the grain structure of the channel region of the second TFT is the same as the second grain structure.  
   
   
       17 . The flat panel display as claimed in  claim 11 , wherein the flat panel display is an active matrix organic light-emitting panel display or active matrix polymer light-emitting panel display.  
   
   
       18 . A flat panel display comprising a plurality of sub-pixels, each of the sub-pixels comprising: 
 a driving TFT, a channel region of the driving TFT comprising a dendrite grain structure; and    a switching TFT, a channel region of the switching TFT comprising a grain structure different from the dendrite grain structure.    
   
   
       19 . The flat panel display as claimed in  claim 18 , wherein the channel region of each of the switching TFTs comprises a columnar grain structure.  
   
   
       20 . The flat panel display as claimed in  claim 18 , wherein the flat panel display further comprises a periphery circuit area, and the periphery circuit area comprises at least a peripheral driving TFT having a channel region that has a grain structure different from the dendrite grain structure.  
   
   
       21 . The flat panel display as claimed in  claim 20 , wherein the channel region of the peripheral driving TFT comprises a columnar grain structure.  
   
   
       22 . The flat panel display as claimed in  claim 18 , wherein the standard deviation of the carrier mobility in the channel regions of the driving TFTs is smaller than the standard deviation of the carrier mobility in the channel regions of the switching TFTs.