Bus system and semiconductor integrated circuit

Abstract

A technology for allowing easy handling of a change in the address range of the subject of access or any of bus masters is provided. There is provided an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information that has been preset in correspondence to the subject of access and to address information corresponding thereto and capable of determining, by referencing the table, the presence or absence of an access right for each of the bus masters based on the subject-of-access information of each of the bus masters and on address information outputted from the bus master. Since the table is shared among the plurality of bus masters, when the address range of the subject of access or any of the bus masters is changed, the table may be rewritten appropriately. This allows, when a plurality of bus masters are connected to a common bus, easy handling of a change in the address range of the subject of access or any of the bus masters.

1 - 7 . (canceled)  
   
   
       8 . A bus system comprising: 
 an internal bus coupled to a plurality of bus masters; and    an address access controlling unit coupled to said internal bus, including:    an access table shared with said plurality of bus masters and storing access right information;    a first decoder operable to decode bus master information received from said internal bus;    a second decoder operable to decode address information inputted from said internal bus; and    an access right controlling module judging an access right of a said bus master by reference to the access table based on the output of said first and second decoders and, and outputting the result of judging to said internal bus,    wherein the address access controlling unit is operable to determine, by referencing said address table, an access right for each bus master based on said bus master information and address information outputted from said bus master, and    wherein said address access controlling unit controls routing for transferring a packet data transferred via said internal bus to a destination address of said packet.    
   
   
       9 . A bus system according to  claim 8 , wherein each of said plurality of bus masters includes an ID register storing said bus master information which is outputtable to said internal bus as required.  
   
   
       10 . A bus system according to  claim 9 , wherein said internal bus includes an address bus, a data bus, a control bus and an ID number bus, and 
 wherein said address access controlling unit couples to said address bus for inputting said address information and said ID number bus for inputting said bus master information.    
   
   
       11 . A semiconductor integrated circuit formed over a single semiconductor substrate and including a bus system which comprises: 
 an internal bus coupled to a plurality of bus masters; and    an address controlling module including:    an address table used for said bus masters, storing access right information;    a first decode unit operable to decode a bus master information received from said internal bus;    a second decode unit operable to decode address information inputted from said internal bus; and    an access judgment module detecting access right information of said address table specified by an output of said first decode unit and an output of said second decode unit and outputting judgment information of the access right to said internal bus,    wherein the address controlling module is operable to judge an access right for each bus master based on said bus master information and address information outputted from said bus master by referencing said table, and    wherein said address controlling module is operable to route for transferring a packet which can be transferred via said bus to a destination address of said packet.    
   
   
       12 . A semiconductor integrated circuit according to  claim 11 , 
 wherein said plurality of bus masters include a central processing unit, and    wherein said address table is rewritable by said central processing unit.    
   
   
       13 . A semiconductor integrated circuit according to  claim 12 , wherein the bus master information is a process ID used by said central processing unit for memory management.  
   
   
       14 . A semiconductor integrated circuit according to  claim 13 , 
 wherein said address table includes an access right information of an external memory unit, and    wherein said external memory unit is accessed by an input/output unit coupled to said internal bus.    
   
   
       15 . A semiconductor integrated circuit including a bus system which comprises: 
 an internal bus coupled to a plurality of bus masters; and    an address controlling unit including:    an access table shared with said plurality of bus masters and storing access right information;    wherein the address controlling unit is operable to control a bus access by referencing said address table,    wherein said address controlling unit inputs bus master information and address information from a bus master, references said access table by using said bus master information and said address information, and determines an access right of said bus master, and    wherein the subject-of-access information contained in said central processing unit is a process ID used by said central processing unit for memory management.    
   
   
       16 . A semiconductor integrated circuit including a bus system according to  claim 15 , wherein said address controlling unit has a routing function for transferring a packet data to a module based on said address information via said internal bus.  
   
   
       17 . A semiconductor integrated circuit according to  claim 15 , 
 wherein said plurality of bus masters include a central processing unit, and said access table in said address controlling unit is rewritable by said central processing unit.    
   
   
       18 . A semiconductor integrated circuit according to  claim 15 ,