Semiconductor integrated circuit device, data processing system and memory system

Abstract

The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and an output terminal for producing a signal formed in an internal circuit in response to the input signal or fed through the input terminal, wherein among the plurality of semiconductor integrated circuit devices, the output terminal of the semiconductor integrated circuit device in the preceding stage and the corresponding input terminal of the semiconductor integrated circuit device of the next stage are connected together.

1 . A semiconductor memory module that includes a plurality of semiconductor memory devices comprising: 
 a clock input terminal configured to receive a timing signal;    a data input terminal configured to receive a data to be stored in any one of the plurality of semiconductor memory devices; and    a instruction input terminal configured to receive a command for determining a state of operation and address information for determining a storing position of the data in any one the plurality of semiconductor memory devices,    wherein the semiconductor memory module further includes output terminals corresponding to the clock input terminal, the data input terminal and the instruction input terminal, and    each of the output terminals is configured to produce a signal formed by the internal circuit in response to the input signal or a signal fed through the input terminal,    wherein the command, the data, the address where the data exists and the timing signal output from the output terminals are re-adjusted by a timing signal reproduced therein.    
   
   
       2 . A semiconductor memory module according to  claim 1 , 
 wherein the timing signal that is re-adjusted is formed by a phase locked loop circuit that receives a reference timing signal.    
   
   
       3 . A semiconductor memory module according to  claim 2 , 
 wherein the reference timing signal is input from an external unit.