Wafer alignment apparatus

Abstract

In a method of aligning a wafer, which is capable of precisely and rapidly aligning the wafer, and a wafer alignment apparatus using the method of aligning the wafer, a first wafer is aligned to form a first template pattern corresponding to an image of the first wafer. Image data of a second wafer is inputted. A kind of the second wafer is different from that of the first wafer. A second template pattern is formed by transforming the first template pattern in response to the image data of the second wafer. The second wafer is then aligned in response to the second template pattern. Accordingly, the template pattern is formed using the image data to align the wafer although wafers having different images are inspected, thereby rapidly forming the template pattern.

1 - 12 . (canceled)  
   
   
       13 . A wafer alignment apparatus, comprising: 
 a wafer transport unit adapted to align a wafer;    a photoelectric transforming unit adapted to transform a two-dimensional image of the wafer into a one-dimensional electrical signal;    an image signal processing unit adapted to transform the one-dimensional electrical signal to a digitized template pattern;    a memory unit adapted to store the template pattern;    an input unit adapted to provide image data of a wafer to be aligned;    an encoder adapted to encode the image data to form template data;    a processor adapted to process the template data and the template pattern to form a modified template pattern; and    a controlling unit adapted to control the wafer transport unit and the processor.    
   
   
       14 . The wafer alignment apparatus as claimed in  claim 13 , further comprising a display unit adapted to receive the template pattern from the processor and to display the two-dimensional image of the wafer.  
   
   
       15 . The wafer alignment apparatus as claimed in  claim 13 , wherein the image signal processing unit further comprises: 
 an analog-digital converter adapted to sample the one-dimensional electrical signal with respect to a time series to quantize the sampled electrical signal to encode the quantized electrical signal to a digitized image signal, thereby defining a pixel;    a color separating unit adapted to separate each of red, green and blue signals from the digitized image; and    a gray-scale converting circuit adapted to convert the separated red, green and blue signals to a template pattern corresponding to an intensity of a gray-scale of the pixel.    
   
   
       16 . The wafer alignment apparatus as claimed in  claim 13 , wherein the processor further comprises: 
 a data selecting part adapted to output outputting the template data or the template pattern in response to a control signal of the controlling part;    a comparing part adapted to compare the template pattern with the output signal of the data selecting part to output difference data;    an interpolating part adapted to interpolate the template pattern in response to the difference data;    a pattern forming part adapted to form a new template pattern in response to the interpolated template pattern; and    a calculating part adapted to compare the difference data with deviation deterministic data stored in the memory unit.    
   
   
       17 . The wafer alignment apparatus as claimed in  claim 16 , wherein the processor further comprises an equalizing part adapted to equalize image distribution of the template pattern and the output signal of the data selecting part.  
   
   
       18 . The wafer alignment apparatus as claimed in  claim 16 , wherein the processor further comprises a thresholding part adapted to binarize the template pattern and the output signal of the data selecting part into black and white image data using a threshold value.  
   
   
       19 . The wafer alignment apparatus as claimed in  claim 13 , wherein the memory unit is adapted to store a template pattern corresponding to a kind of the wafer and deviation deterministic data corresponding to a kind and an alignment of the wafer.  
   
   
       20 . The wafer alignment apparatus as claimed in  claim 19 , wherein the template pattern comprises a plurality of template patterns.  
   
   
       21 . A wafer alignment apparatus, comprising: 
 a wafer transport unit adapted to align a wafer;    an image processor adapted to process a template pattern from an image of the wafer on the wafer transport unit;    an encoder adapted to encode image data of a wafer to be aligned to form template data;    a processor adapted to generate a modified template pattern in accordance with the template pattern from the image processor and the template data from the encoder; and    a controlling unit adapted to control the wafer transport unit and the processor.    
   
   
       22 . The apparatus as claimed in  claim 21 , further comprising an imaging system adapted to illuminate the wafer on the wafer transport unit, the controlling unit further being adapted to control the imaging system.  
   
   
       23 . The apparatus as claimed in  claim 21 , further comprising a memory unit adapted to store the template pattern and the template data.  
   
   
       24 . The apparatus as claimed in  claim 23 , wherein the memory unit is adapted to store a plurality of template patterns.  
   
   
       25 . The apparatus as claimed in  claim 21 , wherein the processor is adapted to compare the template data with the template pattern to form difference data and to generate the modified template pattern in response to the difference data.  
   
   
       26 . The apparatus as claimed in  claim 25 , wherein the processor is adapted to interpolate the template pattern in response to the difference data to form interpolated data corresponding to a new pixel between pixels of a cell in the template pattern.  
   
   
       27 . The apparatus as claimed in  claim 21 , wherein the image processor is adapted to transform a two-dimensional image of the wafer to a one-dimensional electrical signal and to digitize the one-dimensional electrical signal.  
   
   
       28 . The apparatus as claimed in  claim 27 , wherein the processor is further adapted to quantize an intensity of the pixel to a predetermined level to encode the quantized intensity to form an image pattern, the intensity corresponding to a brightness of the pixel, to calculate difference data corresponding to a difference between the image pattern and the modified template pattern, and to determine whether the difference data is less than or equal to a deviation.  
   
   
       29 . The apparatus as claimed in  claim 28 , wherein the controlling unit is further adapted to unload the second wafer when the difference is greater than the deviation.  
   
   
       30 . The apparatus as claimed in  claim 21 , wherein the image data includes at least one of a horizontal width of a unit cell, a vertical length of a unit cell, a width of a raw decoder region, a width of a column decoder region, a width of a sense amplifier region, and a width of a sub-word driver region.