Integrated electronic chip and interconnect device and process for making the same

Abstract

A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads. This method permits fabrication of a high-density packaged device with reduced cost.

1 - 26 . (canceled)  
     
     
         27 . An integrated structure including a semiconductor device and connector structures for connecting the semiconductor device to a motherboard, the integrated structure comprising: 
 a first layer having a first set of conductors disposed therein, the first layer having an upper surface and a lower surface, the first set of conductors connecting to bonding pads disposed on the lower surface, the bonding pads being spaced with respect to each other with a first spacing distance in accordance with a required spacing of connections to the motherboard;    the semiconductor device;    a second layer disposed on the semiconductor device and in contact therewith, the second layer having a second set of conductors disposed therein connecting to the semiconductor device, the second layer facing the first layer;    a plurality of connectors connecting the first set of conductors to the second set of conductors, said connectors being a set of C4 connectors, said connectors being spaced with respect to each other with a second spacing distance less than the first spacing distance;    a support structure attached to the upper surface of the first layer and surrounding the semiconductor device, a gap between said support structure and the semiconductor device being filled with a fill material; and    connector structures connected to the bonding pads.    
     
     
         28 . An integrated structure according to  claim 27 , wherein the connector structures form one of a pin grid array (PGA), a ball grid array (BGA), a C4 array and a land grid array (LGA).  
     
     
         29 . An integrated structure according to  claim 27 , wherein the motherboard is characterized by a thermal coefficient of expansion (TCE), and the support structure is provided with a TCE approximately that of the motherboard.  
     
     
         30 . An integrated structure according to  claim 27 , wherein the support structure has an area corresponding to an area occupied by the bonding pads.  
     
     
         31 . An integrated structure according to  claim 27 , wherein the fill material fills a gap between the semiconductor device and the first layer surrounding the C4 connectors.  
     
     
         32 . An integrated structure including a semiconductor device and connector structures for connecting the semiconductor device to a motherboard, the integrated structure comprising: 
 a first layer having a first set of conductors disposed therein, the first layer having an upper surface and a lower surface, the first set of conductors connecting to bonding pads disposed on the lower surface, the bonding pads being spaced with respect to each other with a first spacing distance in accordance with a required spacing of connections to the motherboard;    the semiconductor device;    a second layer disposed on the semiconductor device and in contact therewith, the second layer having a second set of conductors disposed therein connecting to the semiconductor device, the second layer facing the first layer;    a plurality of connectors connecting the first set of conductors to the second set of conductors, said connectors being a set of stud/via connectors, said connectors being spaced with respect to each other with a second spacing distance less than the first spacing distance;    a support structure attached to the upper surface of the first layer and surrounding the semiconductor device, a gap between said support structure and the semiconductor device being filled with a fill material; and    connector structures connected to the bonding pads.    
     
     
         33 . An integrated structure according to  claim 32 , wherein the connector structures form one of a pin grid array (PGA), a ball grid array (BGA), a C4 array and a land grid array (LGA).  
     
     
         34 . An integrated structure according to  claim 32 , wherein the motherboard is characterized by a thermal coefficient of expansion (TCE), and the support structure is provided with a TCE approximately that of the motherboard.  
     
     
         35 . An integrated structure according to  claim 32 , wherein the support structure has an area corresponding to an area occupied by the bonding pads.  
     
     
         36 . An integrated structure according to  claim 32 , wherein the fill material fills a gap between the semiconductor device and the first layer surrounding the stud/via connectors.