Chip packaging structure

Abstract

A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

1 . A chip packaging structure, comprising: 
 a chip having a first passivation layer and at least a bonding pad, wherein the bonding pad is exposed by the first passivation layer and the first passivation layer has at least a recess, the whole recess has a sidewall and a bottom surface being exposed;    a redistribution layer formed over the first passivation layer, wherein the redistribution layer electrically connects with the bonding pad and extends from the bonding pad to the recess, and the redistribution layer in the recess comprises a sidewall portion and a bottom portion that are respectively in contact with the sidewall and the bottom surface of the recess;    a second passivation layer formed over the first passivation layer and the redistribution layer, wherein the second passivation layer has an opening that exposes the redistribution layer above the recess;    an under-bump-metallurgy layer formed on the redistribution layer in the opening of the second passivation layer, wherein the under-bump-metallurgy layer is in contact with the sidewall portion and the bottom portion of the of the redistribution layer in the recess, and extends over an upper surface of the second passivation layer; and    at least a bump disposed inside the opening and electrically connected to the redistribution layer above the recess.    
     
     
         2 . The chip packaging structure of  claim 1 , wherein the recess has an obtuse angle and is formed between the sidewall of the recess and the bottom surface of the recess.  
     
     
         3 . The chip structure of  claim 1 , wherein the under-bump-metallurgy layer further comprises: 
 a first metallic layer formed over the opening-exposed redistribution layer; and    a second metallic layer formed over the first metallic layer.    
     
     
         4 . The chip structure of  claim 3 , wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium.  
     
     
         5 . The chip structure of  claim 3 , wherein a material constituting the second metallic layer comprises copper.  
     
     
         6 . The chip structure of  claim 3 , wherein the under-bump-metallurgy layer further comprises at least an electroplated layer formed over the second metallic layer and the electroplated layer is selected from the group consisting of an electroplated copper layer, an electroplated nickel layer, an electroless nickel layer, an electroless plated gold layer and combination thereof.  
     
     
         7 . The chip packaging structure of  claim 1 , wherein the under-bump-metallurgy layer further comprises: 
 a first metallic layer formed over the opening-exposed redistribution layer;    a second metallic layer formed over the first metallic layer; and    a third metallic layer formed over the second metallic layer.    
     
     
         8 . The chip packaging structure of  claim 7 , wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium.  
     
     
         9 . The chip packaging structure of  claim 7 , wherein a material constituting the second metallic layer is selected from the group consisting of nickel-vanadium alloy and copper-chromium alloy.  
     
     
         10 . The chip packaging structure of  claim 7 , wherein a material constituting the third metallic layer comprises copper.  
     
     
         11 . The chip packaging structure of  claim 7 , wherein the under-bump-metallurgy layer further comprises at least an electroplated layer formed over the third metallic layer and the electroplated layer is selected from the group consisting of an electroplated copper layer, an electroplated nickel layer, an electroplated gold layer and combination thereof.  
     
     
         12 . The chip packaging structure of  claim 1 , wherein the redistribution layer further comprises: 
 a first metallic layer formed over the first passivation layer; and    a second metallic layer formed over the first metallic layer.    
     
     
         13 . The chip packaging structure of  claim 12 , wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium.  
     
     
         14 . The chip packaging structure of  claim 12 , wherein a material constituting the second metallic layer comprises copper.  
     
     
         15 . The chip packaging structure of  claim 1 , wherein the redistribution layer further comprises: 
 a first metallic layer formed over the first passivation layer;    a second metallic layer formed over the first metallic layer; and    a third metallic layer formed over the second metallic layer.    
     
     
         16 . The chip packaging structure of  claim 15 , wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium.  
     
     
         17 . The chip packaging structure of  claim 15 , wherein a material constituting the second metallic layer is selected from the group consisting of nickel-vanadium alloy and copper-chromium alloy.  
     
     
         18 . The chip packaging structure of  claim 15 , wherein a material constituting the third metallic layer comprises copper.  
     
     
         19 . The chip packaging structure of  claim 1 , wherein an obtuse angle is formed between a sidewall of the opening and a bottom surface of the opening.