Semiconductor device having isolation region and method of manufacturing the same

Abstract

A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

1 . A semiconductor device comprising: an element region isolated by an isolation region formed in a semiconductor layer; first and second MOS transistors formed in the element region, and provided with source and drain regions, one source region and the other drain region being used in common, the first MOS transistor having a first gate electrode provided with a first gate insulating film having a first thickness, the second MOS transistor having a second gate electrode provided with a second gate insulating film having a second thickness thinner than the first thickness; a first channel stopper region formed under the isolation region, the first channel stopper region is separated from the source and drain regions of the first MOS transistor; and a second channel stopper region formed under the isolation region, the second channel stopper region is situated adjacent to the source and drain regions of the second MOS transistor.  
   
   
       2 . The device according to  claim 1 , wherein each of the first and second MOS transistors is a depression type NMOSFET.