Method of manufacturing a semiconductor device

Abstract

In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation pattern to partially fill up the opening. A sacrificial layer is formed on the preliminary polysilicon layer. The sacrificial layer is partially etched to expose a portion of the preliminary polysilicon layer formed on a shoulder portion of the isolation pattern. A first polysilicon layer is formed by etching the exposed portion of the preliminary polysilicon layer to enlarge an upper width of the opening. After the etched sacrificial layer is removed, a second polysilicon layer is formed on the first polysilicon layer to fill up the enlarged opening. Because the upper width of the opening is larger than the lower width, no seam or void would be generated in the second polysilicon layer, therefore improving the electrical characteristics and reliability of the device.

1 . A floating gate structure of a semiconductor device comprising: 
 an outer polysilicon layer having an opening formed therein; and    an inner polysilicon layer with at least a portion of the inner polysilicon layer formed within the opening, the inner polysilicon layer having a lower portion within the opening that is narrower than an upper portion.    
   
   
       2 . The floating gate structure of  claim 1 , further comprising a first dielectric layer formed over the top of the floating gate structure.  
   
   
       3 . The floating gate structure of  claim 2 , further comprising a second dielectric layer interposed between an active region of a substrate and the outer polysilicon layer.  
   
   
       4 . The floating gate structure of  claim 3 , wherein the first dielectric layer is spaced from the second dielectric layer.