Flash memory cell and method for manufacturing the same

Abstract

An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer are patterned to form a plurality of gate lines. Deep ion implantation in a deep portion of the active region is performed using a self-aligned source mask. The active region and the trench region are exposed through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region. Ions are implanted in the common source region using the self-aligned source mask.

1 . A flash memory cell, comprising: 
 a semiconductor substrate having an active region and a trench region;    a first oxide layer, a first polysilicon layer, a second oxide layer, and a second polysilicon layer formed on said semiconductor substrate;    a plurality of trench lines formed parallel to each other;    a plurality of gate lines formed perpendicular to said plurality of trench lines; and    a common source region formed parallel to and between said plurality of gate lines by implanting ions into the active region and the trench region, wherein a depth of ions implanted in the trench region is approximately the same as a depth of ions implanted in the active region.    
     
     
         2 . The flash memory cell according to  claim 1 , wherein the active region is a source region.  
     
     
         3 . The flash memory cell according to  claim 1 , wherein the plurality of trench lines is parallel to a bit line and wherein the plurality of gate lines is parallel to a word line.  
     
     
         4 - 17 . (canceled)