Dormant error checker

Abstract

In accordance with some embodiments, an error checking scheme to check for an error in a memory unit during a dormant state is provided herein.

1 . A chip, comprising: 
 a memory unit to store data; and    an error checking circuit coupled to the memory unit to check its data for an error when it is in a dormant state.    
   
   
       2 . The chip of  claim 1 , in which the memory unit comprises a register in a microprocessor core.  
   
   
       3 . The chip of  claim 1 , in which the error checking circuit comprises a parity checker circuit.  
   
   
       4 . The chip of  claim 3 , in which the parity checker circuit comprises XOR circuits cascaded together to perform a parity function and has a disable capability to save power when the memory unit is in the dormant state.  
   
   
       5 . The chip of  claim 3 , in which the parity checker circuit comprises a plurality of complementary switch sections coupled between cross-coupled pull-up transistors and supply references including a virtual Vss reference.  
   
   
       6 . The chip of  claim 1 , comprising additional error checking circuits coupled to associated memory units, the error checking and additional error checking circuits being coupled to a common controller to initiate error checking when their associated memory units are in dormant states.  
   
   
       7 . The chip of  claim 6 , in which the error checking and additional error checking circuits are to be in dormant states themselves when their associated memory unit circuits are in the dormant states.  
   
   
       8 . A chip, comprising: 
 registers to store data words; and    an error checking circuit for each of the registers to check their data word for an error when it is in a dormant state.    
   
   
       9 . The chip of  claim 8 , in which the at least one register comprises a register in a microprocessor core.  
   
   
       10 . The chip of  claim 8 , in which the error checking circuits comprise parity checking circuits.  
   
   
       11 . The chip of  claim 10 , in which the parity checking circuits each comprise XOR circuits cascaded together to perform a parity function and have a disable capability to save power when their register is in the dormant state.  
   
   
       12 . The chip of  claim 10 , in which the parity checking circuits each comprise a plurality of complementary switch sections coupled between cross-coupled pull-up transistors and supply references including a virtual Vss reference.  
   
   
       13 . The chip of  claim 12 , in which the error checking circuits are to be in dormant states themselves when their associated register is in the dormant state.  
   
   
       14 . A system, comprising: 
 (a) a microprocessor comprising a memory unit to store data, and an error checking circuit coupled to the memory unit to check its data for an error when it is in a dormant state;    (b) an antenna; and    (c) a wireless interface coupled to the microprocessor and to the antenna to communicatively link the microprocessor to a wireless network.    
   
   
       15 . The system of  claim 14 , in which the memory unit comprises a register in a core of the microprocessor.  
   
   
       16 . The system of  claim 14 , in which the error checking circuit comprises a parity checking circuit.  
   
   
       17 . The system of  claim 16 , in which the parity checking circuit comprises XOR circuits cascaded together to perform a parity function and has a disable capability to save power when the memory unit is in the dormant state.  
   
   
       18 . The system of  claim 3 , in which the parity checker circuit comprises a plurality of complementary switch sections coupled between cross-coupled pull-up transistors and supply references including a virtual Vss reference.  
   
   
       19 . The system of  claim 14 , comprising additional error checking circuits coupled to associated memory units, the error checking and additional error checking circuits being coupled to a common controller to initiate error checking when their associated memory units are in dormant states.  
   
   
       20 . The system of  claim 14  comprising a battery to provide supply power to the microprocessor.