Operation-processing device, method for constructing the same, and operation-processing system and method

Abstract

As shown in FIG. 1 , an operation-processing device of the present invention comprises a register array ( 11 ) having plural registers for holding an arbitrary value based on a write address Aw and a write control signal Sw and outputting this value based on a read address Ar, an ALU ( 12 ) for performing operations on this value, a decoder ( 13 ) for decoding an operation instruction from an operation program AP for operating this ALU ( 12 ), and an instruction-execution-controlling portion ( 50 ) for controlling the register array ( 11 ) and the ALU ( 12 ) in order to execute this operation instruction, wherein this instruction-execution-controlling portion ( 50 ) selects one of the registers based on the operation instruction and performs register-to-register addressing processing that, based on a value held by this selected register, selects another register.

1 - 16 . (canceled)  
     
     
         17 . An operation-processing device for performing operation processing based on an operation program for performing register-to-register addressing processing, comprising: 
 plural registers;    a storage portion for storing a compressed program having a different instruction length in which the number of bits of a instruction for specifying the register is reduced beforehand based on a frequency at which said registers are used and a type of each of the registers is written in an instruction structure of said program;    an instruction-decoding portion for reading the compressed program from said storage portion to decode the type of each of the registers and, based on this type of the registers, restore the number of bits of the instruction for specifying said register; and    an instruction execution/operation portion for performing an arbitrary operation by specifying said register based on the instruction having a predetermined length restored by said instruction-decoding portion.    
     
     
         18 . The operation-processing device according to  claim 17 , wherein in a case where N number of registers are used, when said N number of registers are assigned serial numbers of 1 through N, the types of the registers are classified into a group having a higher use frequency of said first through K'th registers and a group having a lower use frequency of said (K+1)'th through N'th registers.  
     
     
         19 . An operation-processing method for performing operation processing based on an operation program for performing register-to-register addressing processing, said method comprising the steps of: 
 storing a compressed program having a different instruction length in which the number of bits of an instruction for specifying the register is reduced beforehand based on a frequency at which said register is used and a type of said registers are written in an instruction structure of said program;    reading the compressed program to decode the register type;    based on this register type, restoring the number of bits of the instruction for specifying said register; and    performing an arbitrary operation by specifying the register based on the restored instruction having a predetermined length.    
     
     
         20 . The operation-processing method according to  claim 19 , wherein in a case where N number of registers are used, when said N number of registers are assigned serial numbers of 1 through N, the types of the registers are classified into a group having a higher use frequency of said first through K'th registers and a group having a lower use frequency of said (K+1)'th through N'th registers.  
     
     
         21 . An operation-processing system comprising: 
 a program creation device for creating a program by editing an instruction for performing register-to-register addressing operation, based on a predetermined programming language on one hand; and    an operation-processing device for performing the register-to-register addressing operation by using said program and plural registers on the other hand,    wherein said program creation device reduces the number of bits of an instruction for specifying the register based on a frequency at which said registers are used and writes a type of each of the registers in an instruction structure of the program, thereby creating a compressed program having a different instruction length; and    wherein said operation-processing device obtains the compressed program created by said program creation device to decode the type of each of the registers and, based on said register type, restores the number of bits of the instruction for specifying the register, to specify the plural registers based on the instruction having a predetermined length, thereby performing arbitrary operation.    
     
     
         22 . The operation-processing system according to  claim 21 , wherein said operation-processing device comprises: 
 plural registers;    a storage portion for storing a compressed program for specifying said register;    an instruction-decoding portion for reading the compressed program from said storage portion to decode the type of each of the registers and, based on this type of each of the registers, restoring the number of bits of the instruction for specifying said register; and    an instruction execution/operation portion for performing an arbitrary operation by specifying said register based on the instruction having a predetermined length restored by said instruction-decoding portion.    
     
     
         23 . The operation-processing system according to  claim 21 , wherein in a case where N number of registers are used, when said N number of registers are assigned serial numbers of 1 through N, the types of the registers are classified into a group having a higher use frequency of said first through K'th registers and a group having a lower use frequency of said (K+1)'th through N'th registers  
     
     
         24 . An operation-processing method comprising the steps of: 
 creating, at a program creation system, a program by editing an instruction for performing register-to-register addressing operation based on a predetermined programming language; and    performing, at a program execution system, said register-to-register addressing operation by using this program and plural registers,    wherein said program creation system reduces the number of bits of an instruction for specifying the register based on a frequency at which said registers are used and writes a type of each of the registers in an instruction structure of this program, thereby creating a compressed program having a different instruction length; and    wherein said program execution system obtains the compressed program created by said program creation system to decode the type of each of the registers, based on said decoded register type, restores the number of bits of the instruction for specifying the register, and specifies the plural registers based on said instruction having a restored predetermined length, thereby performing arbitrary operation.    
     
     
         25 . The operation-processing method according to  claim 24 , wherein in a case where N number of registers are used, when said N number of registers are assigned serial numbers of 1 through N, the types of the registers are classified into a group having a higher use frequency of said first through K'th registers and a group having a lower use frequency of said (K+1)'th through N'th registers.