Multi-Mode Memory

Abstract

A multi-mode memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval is imposed between successive accesses to a given row of the storage cells. Data path circuitry is provided to transfer data between the plurality of storage banks and an external signal path during first and second modes of operation of the memory device. During the first mode of operation a first data item is transferred, in response to a first memory access request, during a first time interval that is not longer than the minimum time interval. During the second mode of operation a plurality of data items are transferred during the first time interval, in response to a plurality of memory access requests.

1 . A memory device comprising: 
 storage banks each including a plurality of rows of storage cells, wherein a minimum time interval is imposed between successive accesses to a selected one of the rows of storage cells;    data path circuitry to transfer data between the storage banks and an external signal path, wherein the memory device is operable in a first mode and a second mode, wherein: 
 during the first mode of operation, a first data item is transferred during a first interval in response to a first memory access request, wherein the first interval is not longer than the minimum time interval; and  
 during the second mode of operation, a plurality of data items are transferred during the first interval in response to a plurality of memory access requests.  
   
   
   
       2 . The memory device of  claim 1  wherein each of the plurality of data items has a smaller granularity than the first data item.  
   
   
       3 . The memory device of  claim 1  wherein the storage banks comprise one or more even-numbered sub-banks and one or more odd-numbered sub-banks.  
   
   
       4 . The memory device of  claim 3  wherein during the second mode of operation, a second data item is transferred in response to a second memory access request and a third data item is transferred in response to a third memory access request.  
   
   
       5 . The memory device of  claim 4  wherein the second memory access request is directed to the one or more even-numbered sub-banks and wherein the third memory access request is directed to the one or more odd-numbered sub-banks.  
   
   
       6 . The memory device of  claim 4  wherein the second data item is transferred during a second interval and wherein the third data item is transferred, following the transfer of the second data item, during a third interval.  
   
   
       7 . The memory device of  claim 6  wherein each of the second and third intervals is not longer than half the minimum time interval.  
   
   
       8 . The memory device of  claim 4  wherein the second data item is transferred during the first interval and wherein the third data item is transferred, concurrently with the transfer of the second data item, during the first interval.  
   
   
       9 . The memory device of  claim 8  wherein the data path circuitry comprises first and second data paths, wherein the second data item is transferred along the first data path and wherein the third data item is transferred along the second data path.  
   
   
       10 . The memory device of  claim 1  wherein each of the plurality of memory access requests comprises: 
 a row activation request including a bank address and a row address;    a column access request including a first column address; and    a precharge request including the bank address.    
   
   
       11 . The memory device of  claim 10  wherein the column access request further comprises a second column address.  
   
   
       12 . The memory device of  claim 11  wherein the second column address comprises a column offset value.  
   
   
       13 . The memory device of  claim 1  wherein the external signal path comprises: 
 a plurality of data lines;    read data strobe lines to carry read data strobe signals output from the memory device, wherein the read data strobe signals are used to time reception of corresponding read data in a memory controller;    write data strobe lines to carry write data strobe signals output from the memory controller, wherein the write data strobe signals are used to time reception of corresponding write data in the memory device; and    data-mask lines to carry respective mask bits wherein each mask bit indicates whether a corresponding byte of data on the data lines is to be written.    
   
   
       14 . A memory device comprising: 
 storage banks each including a plurality of rows of storage cells, wherein a first minimum time interval is imposed between successive row activations in arbitrarily different storage banks;    an interface to access the storage cells, the interface comprising circuitry to receive first and second row activation requests during a first interval, wherein the first interval is not longer than the first minimum time interval.    
   
   
       15 . The memory device of  claim 14  wherein a second minimum time interval is imposed between successive accesses to a selected one of the rows of storage cells, and wherein the interface further comprises circuitry to concurrently receive first and second column addresses during a second interval, wherein the second interval is not longer than half the second minimum time interval.  
   
   
       16 . A memory controller comprising: 
 a read transaction queue to store one or more read access requests;    a write transaction queue to store one or more write access requests;    a queue control logic to queue the read access requests in the read transaction queue and to queue the write access requests in the write transaction queue; and    data path circuitry to transfer data between a host interface and a memory device, wherein the memory device comprises a partitioned storage bank.    
   
   
       17 . The memory controller of  claim 16  wherein the read transaction queue comprises a plurality of read queues, wherein each of the plurality of read queues corresponds to a respective partition of the storage bank.  
   
   
       18 . The memory controller of  claim 16  wherein the write transaction queue comprises a plurality of write queues, wherein each of the plurality of write queues corresponds to a respective partition of the storage bank.  
   
   
       19 . A system comprising: 
 a memory controller;    a memory device operable in a first mode and a second mode; and    data path circuitry to transfer data between the memory device and the memory controller, wherein during the first mode of operation, a first data item is transferred during a first interval in response to a first memory access request, and during the second mode of operation, a plurality of data items are transferred during the first interval in response to a plurality of memory access requests.