Conductive spacers for semiconductor devices and methods of forming

Abstract

A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

1 . A method of forming a conductive spacer on a semiconductor device, comprising: 
 depositing a polysilicon layer on the semiconductor device;    implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area; and    removing the polysilicon layer except for the conductive spacer area.    
   
   
       2 . The method of  claim 1 , further comprising forming silicide on the conductive spacer area to enhance conductivity.  
   
   
       3 . The method of  claim 2 , wherein the silicide comprises nickel silicide.  
   
   
       4 . The method of  claim 1 , wherein the dopant ions comprise boron.  
   
   
       5 . The method of  claim 4 , wherein removing the polysilicon layer comprises a KOH wet etching process.  
   
   
       6 . The method of  claim 1 , wherein the dopant ions comprise arsenic.  
   
   
       7 . The method of  claim 6 , wherein removing the polysilicon layer comprises reactive ion etching.  
   
   
       8 . The method of  claim 1 , wherein implanting the dopant ions comprises implanting the dopant ions at a predetermined angle with respect to a horizontal axis.  
   
   
       9 . The method of  claim 8 , wherein the predetermined angle is between approximately 15 degrees and approximately 60 degrees.  
   
   
       10 . An SRAM cell comprising: 
 a transistor region having a non-conductive spacer on a first side;    a metallization layer; and    a conductive spacer defined on the non-conductive spacer, the conductive spacer forming a cross couple connection below the metallization layer.    
   
   
       11 . A semiconductor device, comprising: 
 a semiconductor substrate;    an n-FET region being disposed on the substrate;    a p-FET region having a first side and a second side, the p-FET region being disposed on the substrate; and    a conductive spacer defined on the first side of the p-FET region.    
   
   
       12 . The semiconductor device of  claim 11 , further comprising a buried oxide layer.  
   
   
       13 . The semiconductor device of  claim 12 , further comprising shallow trench isolation structures positioned between the n-FET and the p-FET regions.  
   
   
       14 . The semiconductor device of  claim 11 , wherein the conductive spacer comprises polysilicon.  
   
   
       15 . The semiconductor device of  claim 11 , wherein the conductive spacer comprises a metal silicide.  
   
   
       16 . The semiconductor device of  claim 11 , wherein the conductive spacer comprises a material selected from the group consisting of cobalt silicide, tungsten silicide, and nickel silicide.  
   
   
       17 . The semiconductor device of  claim 11 , wherein the conductive spacer comprises a material selected from the group consisting of tungsten, tantalum, niobium, and aluminum.  
   
   
       18 . The semiconductor device of  claim 11 , wherein the conductive spacer is adapted for connection to a metallization layer so that a cross couple connection is formed below the metallization layer.