Semiconductor Integrated Circuit

Abstract

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

1 . A semiconductor integrated circuit comprising: 
 a central processing unit; and    a rewritable nonvolatile memory area disposed in an address space of the central processing unit, wherein    the nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages; and    the first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area.    
   
   
       2 . The semiconductor integrated circuit according to  claim 1 , wherein the first nonvolatile memory area is set lower in a distribution of initializing levels of threshold voltages compared with the second nonvolatile memory area to make the maximum variation width of the threshold voltages larger.  
   
   
       3 . The semiconductor integrated circuit according to  claim 1 , wherein the first nonvolatile memory area is made faster in a read speed of memory information compared with the second nonvolatile memory area.  
   
   
       4 . The semiconductor integrated circuit according to  claim 1 , wherein a first nonvolatile memory provided with the first nonvolatile memory area and a second nonvolatile memory provided with the second nonvolatile memory area are separately included.  
   
   
       5 . The semiconductor integrated circuit according to  claim 1 , wherein one nonvolatile memory provided with both the first nonvolatile memory area and the second nonvolatile memory area is included.  
   
   
       6 . The semiconductor integrated circuit according to  claim 3 , wherein the first nonvolatile memory area is used to store a program and the second nonvolatile memory area is used to store data.  
   
   
       7 . A semiconductor integrated circuit comprising: 
 a central processing unit;    a volatile memory;    a first bus thereto the central processing unit and the volatile memory are connected;    a bus controller connected to the first bus; and    a second bus connected to the bus controller, wherein    to the first bus, a first electrically rewritable nonvolatile memory that memorizes information depending on difference of threshold voltages is connected;    to the second bus, a second electrically rewritable nonvolatile memory that memorizes information depending on difference of threshold voltages is connected; and    the first nonvolatile memory is set larger in a maximum variation width of a threshold voltage for memorizing information than that of the second nonvolatile memory.    
   
   
       8 . The semiconductor integrated circuit according to  claim 7 , wherein the first nonvolatile memory area is set lower in a distribution of initializing levels of threshold voltages compared with the second nonvolatile memory area to make the maximum variation width of the threshold voltages larger.  
   
   
       9 . The semiconductor integrated circuit according to  claim 7 , wherein the first nonvolatile memory area is used to store a program that the central processing unit executes and the second nonvolatile memory area is used to store data that are used when the central processing unit executes the program.  
   
   
       10 . The semiconductor integrated circuit according to  claim 9 , wherein the first nonvolatile memory has a first access port that is used in a read access to the first bus and a second access port that is used in a rewrite access of memory information from the second bus, the central processing unit executing an access control for rewriting memory information to a first memory.  
   
   
       11 . The semiconductor integrated circuit according to  claim 10 , wherein an address space to a first nonvolatile memory seen from the first access port and an address space to the first nonvolatile memory seen from the second access port are differentiated.  
   
   
       12 . The semiconductor integrated circuit according to  claim 11 , wherein the central processing unit, when an external interface circuit is connected to the second bus and a rewrite command is externally inputted in the external interface circuit, deciphers the rewrite command and executes a rewrite control program that the first nonvolatile memory holds in accordance with a deciphered result to control a rewrite operation of memory information that the first nonvolatile memory holds.  
   
   
       13 . The semiconductor integrated circuit according to  claim 12 , wherein an ECC circuit capable of detecting and correcting an error to data read from the first access port is disposed between the first access port and the first bus.  
   
   
       14 . The semiconductor integrated circuit according to  claim 9 , wherein 
 the first nonvolatile memory has a number of nonvolatile memory cells and the nonvolatile memory cells each have a memory transistor of which threshold voltage is differentiated depending on a charge retention state of a charge storage area and a select transistor capable of selectively connecting the memory transistor to a bit line;    a gate insulating film of the select transistor is formed thinner than that of a gate insulating film of the memory transistor; and    hot electrons formed owing to a potential difference between a channel formed in a semiconductor area immediately below a gate electrode of the select transistor and a channel formed in a semiconductor area immediately below a charge storage area of the memory transistor are injected in the charge storage area to set a threshold voltage higher to reduce electrons held in the charge storage area to initialize a threshold voltage in a lower direction.    
   
   
       15 . A semiconductor integrated circuit comprising: 
 a central processing unit;    a volatile memory;    a first bus thereto the central processing unit and the volatile memory are connected;    a bus controller connected to the first bus; and    a second bus connected to the bus controller, wherein    a nonvolatile memory is connected to the first bus;    the nonvolatile memory has a first nonvolatile memory area and a second nonvolatile memory area, which store information depending on a difference of threshold voltages; and    the first nonvolatile memory area is set larger in a maximum variation width of a threshold voltage for storing information compared with the second nonvolatile memory area.    
   
   
       16 . The semiconductor integrated circuit according to  claim 15 , wherein the first nonvolatile memory area is set lower in a distribution of initializing levels of threshold voltages compared with the second nonvolatile memory area to make a maximum variation width of the threshold voltages larger.  
   
   
       17 . The semiconductor integrated circuit according to  claim 15 , wherein a read determination level that is imparted to a nonvolatile memory cell when memory information corresponding to a threshold voltage is read from the nonvolatile memory cell in the first nonvolatile memory area is set same as a read determination level that is imparted to a nonvolatile memory cell when memory information corresponding to a threshold voltage is read from the nonvolatile memory cell in the second nonvolatile memory area.  
   
   
       18 . The semiconductor integrated circuit according to  claim 17 , wherein the first nonvolatile memory area is used to store a program that the central processing unit executes and the second nonvolatile memory area is used to store data that are used when the central processing unit executes the program.  
   
   
       19 . The semiconductor integrated circuit according to  claim 18 , wherein each of the first nonvolatile memory area and the second nonvolatile memory area has a hierarchal bit line structure that is made of a plurality of segmented areas, a plurality of first bit lines intrinsic to each of the segmented areas, a second bit line common to the plurality of segmented areas, a select circuit that selects the first bit line from the segmented area and a sense amplifier disposed between an output of the select circuit and the second bit line, wherein 
 a load of each of the first bit lines is smaller in the second nonvolatile memory area than in the first nonvolatile memory area.    
   
   
       20 . The semiconductor integrated circuit according to  claim 18 , wherein the central processing unit, in a read access control to the nonvolatile memory, controls so that the number of access cycles to the second nonvolatile memory area is larger than the number of access cycles to the first nonvolatile memory area.  
   
   
       21 . The semiconductor integrated circuit according to  claim 18 , wherein the nonvolatile memory has a first access port that is used in a read access to the first bus and a second access port that is used in a rewrite access of memory information from the second bus, the central processing unit applying an access control for rewriting memory information to the nonvolatile memory.  
   
   
       22 . The semiconductor integrated circuit according to  claim 21 , wherein an address space to the nonvolatile memory seen from the first access port and an address space to the nonvolatile memory seen from the second access port are differentiated.  
   
   
       23 . The semiconductor integrated circuit according to  claim 22 , wherein the central processing unit, when an external interface circuit is connected to the second bus and a rewrite command is externally inputted in the external interface circuit, deciphers the rewrite command and executes a rewrite control program that the first nonvolatile memory holds in accordance with a deciphered result to control a rewrite operation of memory information that the first nonvolatile memory holds.  
   
   
       24 . The semiconductor integrated circuit according to  claim 22 , wherein an ECC circuit capable of detecting and correcting an error of data read from the first access port is disposed between the first access port and the first bus.  
   
   
       25 . The semiconductor integrated circuit according to  claim 18 , wherein 
 the nonvolatile memory has a number of nonvolatile memory cells and the nonvolatile memory cell has a memory transistor of which threshold voltage is differentiated depending on a charge retention state of a charge storage area and a select transistor capable of selectively connecting the memory transistor to a bit line;    a gate insulating film of the select transistor is formed thinner than a gate insulating film of the memory transistor; and    hot electrons formed owing to a potential difference between a channel formed in a semiconductor area immediately below a gate electrode of the select transistor and a channel formed in a semiconductor area immediately below a charge storage area of the memory transistor are injected in the charge storage area to set a threshold voltage higher to reduce electrons held in the charge storage area to initialize the threshold voltage in a lower direction.    
   
   
       26 . A semiconductor integrated circuit comprising: 
 a central processing unit; and    a rewritable nonvolatile memory area disposed in an address space of the central processing unit, wherein    the nonvolatile memory area includes a first nonvolatile memory area and a second nonvolatile memory area, which store information depending on a difference of a current amount that flows a memory cell;    a memory cell of the first memory area and a memory cell of the second memory area, respectively, have a first state and a second state;    in a first state of the memory cell in the first memory area and a first state of the memory cell of the second memory area, both current amounts that flow the memory cells are contained in a first range;    in a second state of the memory cell in the first memory area, a current amount that flows the memory cell is contained in a second range; and    in a second state of the memory cell in the second memory area, a current amount that flows the memory cell is contained in a third range different from the second range.    
   
   
       27 . The semiconductor integrated circuit according to  claim 26 , wherein the second range and the third range are partially overlapped.  
   
   
       28 . The semiconductor integrated circuit according to  claim 27 , wherein a detection circuit that detects in which range of the first through third ranges a current that flows the memory cell is contained is disposed.