Content addressable memory

Abstract

An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

1 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to the entries and transferring search data in parallel to the respective entries; and   a plurality of match amplifiers, coupled to the respective match lines, each including a precharge circuit for precharging a corresponding match line to a precharge voltage not higher than an intermediate value between a power supply voltage and a ground voltage, an amplifier circuit for comparing a voltage on the corresponding match line with a reference voltage at a voltage level not higher than said precharge voltage, and an isolation gate for isolating the amplifier circuit from the corresponding match line before activation of said amplifier circuit.   
   
   
       2 . The content addressable memory according to  claim 1 , further comprising a reference voltage generating circuit for producing and transmitting said reference voltage to each of said plurality of match amplifiers, wherein
 said isolation gate isolates said reference voltage generating circuit from the amplifier circuit before activation of said amplifier circuit.   
   
   
       3 . The content addressable memory according to  claim 1 , wherein
 said reference voltage is set to a level the same as said precharge voltage.   
   
   
       4 . The content addressable memory according to  claim 1 , wherein
 said content addressable memory has a precharge cycle in which said precharge circuit is activated, a comparison cycle for comparing stored data of each of the entries and the search data on said search data bus, and a match determining cycle in which the amplifier circuit is activated, and   each of the match amplifiers further includes a pull-up current supply circuit for supplying a current to the corresponding match line in said comparison cycle.   
   
   
       5 . The content addressable memory according to  claim 4 , wherein
 said pull-up current supply circuit supplies a current smaller than a one-bit miss current flowing through the corresponding match line when the content addressable memory cell of one bit in the entry is made conductive but larger than an off-leakage current flowing through the corresponding match line when all content addressable memory cells in the entry are non-conductive.   
   
   
       6 . The content addressable memory according to  claim 4 , wherein
 each of the match amplifiers further includes a discharge circuit for discharging the corresponding match line to a voltage level lower than said precharge voltage when said match determining cycle is completed.   
   
   
       7 . The content addressable memory according to  claim 1 , wherein
 said reference voltage is at a same voltage level as said precharge voltage, and   each of the match amplifiers further includes a capacitance element being charged with said reference voltage in an operation of said precharge circuit and holding a charged voltage and transmitting the charged voltage via a corresponding isolation gate to the amplifier circuit in inactivation of said amplifier circuit.   
   
   
       8 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry,   a search data bus coupled in parallel to the entries and transferring search data commonly to the respective entries; and   a plurality of match amplifiers, coupled to the respective match lines, each including an amplifier circuit for comparing a voltage on a corresponding match line with a reference voltage to produce a signal indicating a result of comparison, a precharge circuit for precharging the corresponding match line to a ground voltage level after completion of an amplifying operation of said amplifier circuit, and a pull-up current supply circuit for supplying a current having a restricted current value to the corresponding match line when said precharge circuit is inactive.   
   
   
       9 . The content addressable memory according to  claim 8 , further comprising:
 a current generating circuit including a replica entry having a same construction as a match line discharging path of the entry and having a plurality of replica cells replicating a state having the content addressable memory cell of one bit made conductive in each entry, a replica match line coupled to the plurality of replica cells, and a current supply for supplying a current to said replica match line, wherein   said pull-up current supply circuit includes a transistor element passing a mirror current of the current supplied by said current supply to the corresponding match line.   
   
   
       10 . The content addressable memory according to  claim 8 , further comprising:
 a current generating circuit including (i) a replica entry of a replica of the entry having a same construction as a match line discharging path of said entry and replicating the entry having content addressable memory cells of all bits set to a non-conductive state, (ii) a replica cell of one bit being a replica of the content addressable memory cell and set to a conductive state, (iii) a replica match line coupled to the content addressable memory cells in said replica entry, (iv) a first current mirror type current supply for supplying a current to said replica match line, (v) a second current mirror type current supply for supplying a current to said replica cell, and (vi) a current to voltage converter receiving a mirror current supplied from the first and second current mirror type current supplies and converting a mirror current of received currents into a voltage to produce a bias voltage, wherein   said pull-up current supply circuit includes a transistor element for converting the bias voltage supplied from said current to voltage converter into a current of a magnitude not exceeding said mirror current.   
   
   
       11 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to the entries, for transferring search data in parallel to the entries; and   a plurality of match amplifiers, coupled to the respective match lines, each including (i) a precharge circuit for precharging a corresponding match line to a ground voltage level, and (ii) a pull-up current supply/determination circuit for supplying a current of a restricted current value to the corresponding match line when said precharge circuit is inactive, setting an upper limit of the voltage level of the corresponding match line and producing a signal at a voltage level corresponding to a voltage of the corresponding match line, said restricted current value being smaller than a value of a current flowing through the corresponding match line when the content addressable memory cell of one bit in one entry is conductive, but being larger than a value of a current flowing through the corresponding match line when all content addressable memory cells in a corresponding entry are non-conductive.   
   
   
       12 . The content addressable memory according to  claim 11 , further comprising:
 a constant current supply including (i) a first current supply transistor element producing a current corresponding to a current flowing through a corresponding match line when the content addressable memory cell of one bit in the entry is made conductive, (ii) a second current supply transistor element forming a current mirror circuit with said first current supply transistor element, (iii) a first load transistor element supplied with a current from said second current supply transistor, (iv) a comparing circuit for comparing a reference voltage up to an intermediate voltage level and a voltage on a connection node between said second current supply transistor element and said first load transistor element and supplying a signal corresponding to a result of comparison to a control gate of said first load transistor element, and (v) a discharge element having a same current driving capability as a discharging path of the content addressable memory cell and discharging a current from said first load transistor element, wherein   said pull-up current supply/determination circuit includes a first transistor element forming a current mirror circuit with said first current supply transistor, and a second transistor element connected in series to said first transistor element and causing a flow of a current on a corresponding match line according to an output signal of said comparing circuit.   
   
   
       13 . The content addressable memory according to  claim 12 , wherein
 said pull-up current supply/determination circuit further includes a third transistor element coupled between the first and second transistor elements, and a gate circuit for driving a control gate of said third transistor element according to a voltage on a connection node between the second and third transistor elements and a pull-up instructing signal, and a signal indicating a result of search determination being produced on the connection node between the second and third transistor elements.   
   
   
       14 . The content addressable memory according to  claim 12 , further comprising:
 a buffer circuit for adjusting a level of an output signal of said comparing circuit so as for the second transistor element to have an increased current driving capability, and supply a level adjusted signal to a control gate f said second transistor element.   
   
   
       15 . The content addressable memory according to  claim 12 , wherein
 said first current supply transistor element has a current to voltage conversion function of converting a current into a voltage, and   said content addressable memory further comprises a current converting circuit for converting a level of the voltage produced by said first current supply transistor element so as to reduce a quantity of a current flowing through said first transistor element.   
   
   
       16 . The content addressable memory according to  claim 12 , wherein
 said constant current supply includes:   a replica cell for replicating a discharging path of the content addressable memory cell in conductive state of one bit,   a third transistor element connected between said first current supply transistor element and said replica cell, and being the same in conductivity type as said second transistor element; and   a comparing circuit for comparing a voltage on a connection node between said replica cell and said third transistor element and an intermediate voltage defining an upper limit of a voltage of the match line, and adjusting a control gate voltage of said third transistor element according to a result of comparison.   
   
   
       17 . The content addressable memory according to  claim 16 , wherein
 said replica cell is formed of a resistance element having a resistance value equal to a combined on-resistance of a discharging path of the content addressable memory cell of said one bit.   
   
   
       18 . The content addressable memory according to  claim 11 , wherein
 said constant current supply includes:   a replica entry having a plurality of replica cells replicating a state of the entry having the content addressable memory cell in a conductive state of one bit in said entry, and   a replica match line coupled commonly to the replica cells and being supplied with a current from said first current supply transistor element.   
   
   
       19 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, and each coupled to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to the entries and transferring search data in parallel to each of the entries; and   a plurality of match amplifiers, coupled to the respective match lines, each including (i) a sensing circuit for producing a signal at a voltage level corresponding to a voltage level of a corresponding match line, (ii) a latch circuit for latching a signal corresponding to a voltage level of the match line in a preceding match sensing cycle, and (iii) a charge circuit for selectively supplying a current to the corresponding match line according to a latch signal of said latch circuit in a search operation of searching stored information matching the search data in the entries.   
   
   
       20 . The content addressable memory according to  claim 19 , wherein
 said sensing circuit has a determination reference value for determining the voltage level of the corresponding match line changed according to the latch signal of said latch circuit.   
   
   
       21 . The content addressable memory according to  claim 19 , wherein
 said charge circuit supplies a current smaller than a one-bit miss current flowing through the corresponding match line when the content addressable memory cell of one bit is conductive in one entry but larger than a leakage current flowing through the corresponding match line when the content addressable memory cells of all bits are non-conductive in the one entry.   
   
   
       22 . The content addressable memory according to  claim 19 , wherein
 said charge circuit includes a upper limit clamp setting transistor for preventing rising of the voltage level on the corresponding match line above a predetermined level.   
   
   
       23 . A content addressable memory comprising:
 a plurality of search blocks each including (i) a plurality of entries each including (a) a plurality of content addressable memory cells storing search candidate data, and (b) a match line coupled to said plurality of content addressable memory cells and being driven in a predetermined voltage level direction by a corresponding content addressable memory cell according to a result of match searching with respect to search data; and (ii) a search data bus coupled commonly to said plurality of entries and transferring said search data in parallel;   a plurality of search data input circuits, arranged corresponding to the respective search blocks, each supplying the search data to the search data bus of a corresponding search block; and   an activation control circuit for sequentially activating said plurality of search blocks and said plurality of search data input circuits according to a clock signal.   
   
   
       24 . The content addressable memory according to  claim 23 , wherein
 said plurality of search blocks are divided into a plurality of global blocks having priorities, and   said activation control circuit holds the global block of a lower priority in an inactive state when match with the search data is detected in the global block of a higher priority.   
   
   
       25 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to the entries and transferring search data in parallel to the entries; and   a plurality of match amplifiers, arranged corresponding to the respective match lines, each including (i) a precharge circuit for precharging a reference voltage node and a corresponding match line to a voltage level not higher than an intermediate voltage between a power supply voltage and a ground voltage, (ii) an amplifier circuit having a first node receiving a voltage on the corresponding match line and a second node coupled to said reference voltage node, comparing the voltages on the first and second nodes, and producing a signal indicating a result of comparison, (iii) an isolation gate for isolating the corresponding match line and said reference voltage node from the first and second nodes of said amplifier circuit before activation of said amplifier circuit, respectively, and (iv) a capacitance element for boosting said first node according to a boost instructing signal before the activation of said amplifier circuit after isolation by said isolation gate.   
   
   
       26 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to the entries, for transferring search data in parallel to the entries; and   a plurality of match amplifiers, arranged corresponding to the respective match lines, each including (i) a precharge circuit for precharging a corresponding match line to a precharge voltage level not higher than an intermediate voltage between a power supply voltage and a ground voltage, (ii) an amplifier circuit having a first node receiving a voltage on the corresponding match line and a second node receiving a sense reference voltage produced by changing a voltage at the precharge voltage level through use of a capacitance element, comparing the voltages on the first and second nodes and producing a signal indicating a result of comparison, and (iii) an isolation gate for confining charges on the first and second nodes before activation of said amplifier circuit.   
   
   
       27 . The content addressable memory according to  claim 26 , wherein
 said precharge circuit further precharges said second node via said isolation gate to a precharge voltage not higher than said intermediate voltage level, and   each match amplifier further includes a capacitance element arranged between said second node and said isolation gate, performing a charge pump operation according to a voltage down instructing signal to lower the voltage level of said second node to produce said sense reference voltage, said voltage down instructing signal being activated after isolating by said isolation gate before activation of said amplifier circuit.   
   
   
       28 . The content addressable memory according to  claim 26 , wherein
 said precharge circuit further precharges a reference voltage line coupled to said second node via said isolation gate to a voltage level not higher than the intermediate voltage level, and   each match amplifier further includes a capacitance element arranged on said reference voltage line, and performing a charge pump operation according to a voltage down instructing signal to lower the voltage level of said reference voltage line, said voltage down instructing signal being activated before isolating by said isolation gate after completion of said precharge operation.   
   
   
       29 . The content addressable memory according to  claim 26 , wherein
 said precharge circuit further precharges a reference voltage line coupled to said second node via said isolation gate to a voltage level not higher than the intermediate voltage level, and   each match amplifier further includes a capacitance element, a first transistor for precharging said capacitance element to a ground voltage level in an operation of the precharging, and a second transistor for coupling said capacitance element to said reference voltage line according to a voltage down instructing signal, said voltage down instructing signal being activated before confinement of the charges by said isolation gate.   
   
   
       30 . The content addressable memory according to  claim 26 , further comprising:
 a main voltage down circuit arranged commonly to said plurality of match amplifiers, and supplying said sense reference voltage to the second node of each of the match amplifiers, wherein   said main voltage down circuit includes:   a capacitance element,   a first transistor for precharging said capacitance element to a ground voltage level in the precharging operation of the precharge circuit,   a second transistor for precharging an output node coupled to said plurality of match amplifiers to a voltage level not higher than the intermediate voltage level in the precharging operation of the precharge circuit, and   a third transistor for coupling said output node to said capacitance element after completion of said precharging operation of the precharge circuit; and   said output node is coupled to said second node via the isolation gate of each match amplifier.   
   
   
       31 . The content addressable memory according to  claim 30 , wherein
 each of the match amplifiers further includes an equalize transistor for electrically short-circuiting the first and second nodes after completion of the amplifying operation of the amplifier circuit.   
   
   
       32 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled in parallel to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to said entries and transferring search data commonly to the entries; and   a plurality of match amplifiers, coupled to the respective match lines, each including (i) a precharge circuit for precharging a corresponding match line to a precharge voltage level not higher than an intermediate voltage between a power supply voltage and a ground voltage, (ii) an amplifier circuit for comparing a voltage on the corresponding match line and a reference voltage at a same voltage level as the precharge voltage level and producing a signal indicating a result of comparison, and (iii) a capacitance element for supplying accumulated charges to the corresponding match lines when the search data on said search data bus is compared with stored data of each entry.   
   
   
       33 . The content addressable memory according to  claim 32 , wherein
 the precharge voltage and the reference voltage are supplied from a common power supply, and   each match amplifier further includes a reference capacitance element charged by said precharge voltage in the precharging operation by said precharge circuit, and a charged voltage of said reference capacitance element is transmitted as said reference voltage to said each amplifier circuit.   
   
   
       34 . The content addressable memory according to  claim 32 , wherein
 each match amplifier further includes:   a first transistor element coupled between said capacitance element and the corresponding match line, being made conductive to supply the charges of said capacitance element to the corresponding match line when said search data is transferred, and being turned off when said amplifier circuit is active, and   a second transistor element for charging said capacitance element to the power supply voltage level when said first transistor element is non-conductive while the amplifier circuit is active.   
   
   
       35 . A content addressable memory comprising:
 a plurality of entries each having a plurality of content addressable memory cells;   a plurality of match lines, arranged corresponding to the respective entries, each coupled in parallel to the content addressable memory cells in a corresponding entry;   a search data bus coupled in parallel to the entries, for transferring search data in parallel to the entries;   a plurality of match amplifiers, coupled to the respective match lines, each including (i) a precharge circuit coupled to a corresponding match line, for precharging the corresponding match line to a ground voltage level; and a pull-up current supply/determination circuits for, in an operation of comparison between the search data of said search data bus and stored data of a corresponding entry, supplying a current of a restricted current value to the corresponding match line, clamping an upper limit value of a voltage level of the corresponding match line below a predetermined value and producing a signal corresponding to the voltage level of the corresponding match line on an internal node.   
   
   
       36 . The content addressable memory according to  claim 35 , wherein
 said restricted current value is smaller than a value of a current flowing when the content addressable memory cell of one bit is conductive in one entry, but is larger than a current flowing from the corresponding match line through one entry when all the content addressable memory cells in said one entry are non-conductive.   
   
   
       37 . The content addressable memory according to  claim 35 , wherein
 each of the match amplifiers further includes a capacitance element for supplying charged charges to the corresponding match line.   
   
   
       38 . The content addressable memory according to  claim 35 , wherein
 said pull-up current supply/determination circuit includes:   a current supply transistor element made conductive complementarily with a first transistor element forming said precharge circuit, and supplying a current, and   a clamping transistor element receiving a bias voltage on a gate, for supplying the current supplied from said current supply transistor element to the corresponding match line.   
   
   
       39 . The content addressable memory according to  claim 38 , wherein
 said pull-up current supply/determination circuit further includes:   a second transistor element connected between said current supply transistor element and said clamping transistor element, and   a gate circuit for selectively making said second transistor element conductive according to a voltage on a connection node between said second transistor element and said clamping transistor element and to a pull-up instruction.