Hard Mask Layer Stack And A Method Of Patterning

Abstract

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO 2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

1 . A semiconductor device having a layer stack comprising: 
 a patterned layer;    a carbon layer disposed above the patterned layer, wherein the carbon layer is in contact with the patterned layer; and    a cover layer disposed on top of the carbon layer.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the carbon layer includes voids in the spaces between patterns in the patterned layer.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the carbon layer is made of elemental carbon.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the cover layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the patterned layer includes line patterns.  
   
   
       6 . The semiconductor device of  claim 1 , wherein the patterned layer includes patterns with a thickness of more than 100 nm.  
   
   
       7 . A hard mask layer stack for patterning a layer to be patterned, comprising: 
 a carbon layer disposed above the layer to be patterned;    an intermediate layer disposed on top of the carbon layer; and    a cover layer disposed on top of the intermediate layer;    wherein the intermediate layer is thicker than the cover layer.    
   
   
       8 . The hard mask layer stack of  claim 7 , wherein the carbon layer and the intermediate layer exist in an unpatterned manner beneath the cover layer.  
   
   
       9 . The hard mask layer stack of  claim 7 , wherein the carbon layer is made of elemental carbon.  
   
   
       10 . The hard mask layer stack of  claim 7 , wherein the carbon layer is thicker than the intermediate layer.  
   
   
       11 . The hard mask layer stack of  claim 7 , wherein the cover layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       12 . The hard mask layer stack of  claim 7 , wherein the intermediate layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       13 . The hard mask layer stack of  claim 7 , wherein the intermediate layer is thicker than the cover layer.  
   
   
       14 . The hard mask layer stack of  claim 7 , wherein the stack has a thickness greater than 100 nm.  
   
   
       15 . The hard mask layer stack of  claim 7 , wherein a photoresist layer is disposed in contact with the cover layer.  
   
   
       16 . A hard mask layer stack comprising: 
 a carbon layer disposed above and in contact with a patterned layer, the carbon layer comprising voids in the spaces between patterns in the patterned layer; and    a cover layer disposed on top of the carbon layer.    
   
   
       17 . The hard mask layer stack of  claim 16 , wherein the carbon layer is made of elemental carbon.  
   
   
       18 . The hard mask layer stack of  claim 16 , wherein the cover layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       19 . A method of patterning a layer comprising: 
 providing a hard mask layer stack on top of a patterned layer, the hard mask layer stack comprising a carbon layer disposed on top of the patterned layer;    removing the hard mask layer stack from above a predetermined section of the patterned layer; and    removing the patterns from the predetermined section of the patterned layer.    
   
   
       20 . The method of  claim 19 , wherein removing the hard mask layer stack from above the predetermined section of the patterned layer includes: 
 providing a photoresist layer on top of the cover layer and removing the photoresist layer from above the predetermined section of the patterned layer; and    etching the hard mask layer stack using the patterned photoresist layer as an etching mask.    
   
   
       21 . The method of  claim 19 , further comprising: 
 removing the hard mask layer stack after removing the patterns from the predetermined section of the patterned layer; and    using the patterned layer as an etching mask for etching a layer stack beneath the patterned layer.    
   
   
       22 . The method of  claim 21 , wherein the layer stack beneath the patterned layer includes at least one conductive layer and wherein patterns formed by etching the layer stack beneath the patterned layer include conductive lines of a semiconductor device.  
   
   
       23 . A method of manufacturing an integrated circuit comprising: 
 forming a first hard mask on top of a conductive layer stack and patterning the first hard mask to form line structures with an equal distance to each other across an array region;    removing predetermined line structures from the first hard mask using a second hard mask to form a modified first hard mask; and    forming conductive lines using the modified first hard mask.    
   
   
       24 . The method of  claim 23 , wherein the second hard mask includes a carbon layer disposed on top and in contact with the first hard mask.  
   
   
       25 . The method of  claim 24 , wherein the second hard mask further includes a cover layer disposed on top of the carbon layer.  
   
   
       26 . The method of  claim 25 , wherein the cover layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       27 . The method of  claim 23 , wherein forming conductive lines includes etching the conductive layer stack using the modified first hard mask as an etch mask.  
   
   
       28 . A method for patterning a layer to be patterned, comprising: 
 providing a hard mask layer stack on top of a layer to be patterned, the hard mask layer stack comprising a cover layer disposed as the uppermost layer;    removing the cover layer from above a predetermined section of the layer to be patterned;    thereafter patterning the cover layer;    etching the hard mask layer stack and the layer to be patterned using the patterned cover layer as an etching mask.    
   
   
       29 . The method of  claim 28 , wherein the hard mask layer stack further includes a carbon layer disposed on top of the layer to be patterned and an intermediate layer disposed on top of the carbon layer and beneath the cover layer.  
   
   
       30 . The method of  claim 28 , wherein patterning the cover layer includes: 
 providing a photoresist layer on top of the cover layer after removing the cover layer from above the predetermined section and patterning the photoresist layer;    etching the cover layer using the patterned photoresist layer as an etching mask; and    removing the patterned photoresist layer after etching the cover layer.    
   
   
       31 . The method of  claim 28 , wherein the intermediate layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       32 . The method of  claim 28 , wherein the cover layer includes a material selected from a group comprising silicon oxynitride, silicon oxide, silicon nitride, and silicon.  
   
   
       33 . The method of  claim 28 , further comprising: 
 removing the hard mask layer stack after removing the patterns from the predetermined section of the patterned layer; and    using the patterned layer as an etching mask for etching a layer stack beneath the patterned layer.    
   
   
       34 . The method of  claim 33 , wherein the layer stack beneath the patterned layer includes at least one conductive layer and wherein patterns formed by etching the layer stack beneath the patterned layer include conductive lines of a semiconductor device.  
   
   
       35 . The method of  claim 34 , wherein the conductive lines form a line/space pattern and are arranged in subsets, wherein the conductive lines have an equal first distance to each other within the subsets and wherein the subsets are arranged to each other with a second distance being larger than the first distance.  
   
   
       36 . A method of manufacturing an integrated circuit comprising: 
 forming a first hard mask on top of a conductive layer stack;    forming a second hard mask on top of the first hard mask and removing the second hard mask from over a predetermined section of an array region;    thereafter patterning the second hard mask to form line structures in the second hard mask;    transferring the patterns in the second hard mask into the first hard mask; and    forming the conductive lines using the patterns in the first hard mask.    
   
   
       37 . The method of  claim 36 , wherein the line structures in the second hard mask are formed with an equal distance to each other in an array region.  
   
   
       38 . The method of  claim 36 , wherein the second hard mask includes a carbon layer disposed on top and in contact with the first hard mask.  
   
   
       39 . The method of  claim 38 , wherein the second hard mask further includes an intermediate layer disposed on top of the carbon layer and a cover layer disposed on top of the intermediate layer.  
   
   
       40 . The method of  claim 36 , wherein forming conductive lines includes etching the conductive layer stack using the modified first hard mask as an etch mask.