Circuit output stage protection system

Abstract

An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.

1 . An integrated circuit (IC) output protection system, comprising: 
 a first output stage capable of receiving an output of a logic core, wherein an operating voltage of the first output stage is substantially equivalent to an operating voltage of the logic core; and    a second output stage coupled to the first output stage, wherein the operating voltage of the first output stage is lower than an operating voltage of the second output stage and the second output stage causes the first output stage to operate substantially below a voltage rating of the first output stage.    
   
   
       2 . The IC output protection system of  claim 1 , wherein the first output stage includes a first transistor and the second output stage includes a second transistor coupled to the first transistor  
   
   
       3 . The IC output protection system of  claim 2 , further comprising: a biasing circuit to bias the second transistor in the second output stage such that a gate to source voltage of the first transistor does not substantially exceed a voltage rating of the first output stage.  
   
   
       4 . The IC output protection system of  claim 2 , wherein the second output stage further includes a third transistor coupled to the second transistor, wherein the third transistor biases the second transistor to operate in a second saturation region.  
   
   
       5 . The IC output protection system of  claim 4 , wherein the first transistor, the second transistor, and the third transistor are NMOS devices.  
   
   
       6 . The IC output protection system of  claim 2 , wherein at least one of a gate to source voltage of the first transistor, a gate to drain voltage of the first transistor, or a source to drain voltage of the first transistor does not substantially exceed a voltage rating of the first output stage.  
   
   
       7 . The IC output protection system of  claim 2 , wherein at least one of a gate to source voltage of the second transistor, a gate to drain voltage of the second transistor, or a source to drain voltage of the second transistor does not substantially exceed a voltage rating of the second output stage.  
   
   
       8 . The IC output protection system of  claim 1 , wherein the first output stage comprises at least one 1.2V device, and the second output stage comprises at least one 2.5V device.  
   
   
       9 . The IC output stage protection system of  claim 2 , wherein a voltage difference between any two terminals of the first transistor does not exceed approximately 1.32 V.  
   
   
       10 . The IC output stage protection system of  claim 2 , wherein a voltage difference between any two terminals of the second transistor does not exceed approximately 2.75 V.  
   
   
       11 . The IC output protection system of  claim 1 , wherein the second output stage causes a first transistor in the first output stage to operate in a first saturation region.  
   
   
       12 . An integrated circuit (IC) output protection system, comprising: 
 a first output stage configured to receive an output of a logic core;    a second output stage coupled between the first output stage and an output node, wherein the operating voltage of the first output stage is lower than an operating voltage of the second output stage; and    at least one diode coupled between the output node and the second output stage, wherein the at least one diode causes at least one of: the first output stage to substantially operate within a first device voltage rating or the second output stage to substantially operate with a second device voltage rating.    
   
   
       13 . The IC output protection system of  claim 12 , wherein the first output stage includes a first transistor and the second output stage includes a second transistor coupled to the first transistor  
   
   
       14 . The IC output protection system of  claim 13 , further comprising: a biasing circuit to bias the second transistor in the second output stage such that a gate to source voltage of the first transistor does not substantially exceed a voltage rating of the first output stage.  
   
   
       15 . The IC output protection system of  claim 13 , wherein the second output stage further includes a third transistor coupled to the second transistor, wherein the third transistor biases the second transistor to operate in a second saturation region.  
   
   
       16 . The IC output protection system of  claim 13 , wherein the first transistor, the second transistor, and the third transistor are NMOS devices.  
   
   
       17 . The IC output protection system of  claim 13 , wherein at least one of a gate to source voltage of the first transistor, a gate to drain voltage of the first transistor, or a source to drain voltage of the first transistor does not substantially exceed a voltage rating of the first output stage.  
   
   
       18 . The IC output protection system of  claim 13 , wherein at least one of a gate to source voltage of the second transistor, a gate to drain voltage of the second transistor, or a source to drain voltage of the second transistor does not substantially exceed a voltage rating of the second output stage.  
   
   
       19 . The IC output protection system of  claim 12 , wherein the first output stage comprises at least one 1.2V device, and the second output stage comprises at least one 2.5V device.  
   
   
       20 . The IC output stage protection system of  claim 13 , wherein a voltage difference between any two terminals of the first transistor does not exceed approximately 1.32 V.  
   
   
       21 . The IC output stage protection system of  claim 13 , wherein a voltage difference between any two terminals of the second transistor does not exceed approximately 2.75 V.  
   
   
       22 . The IC output protection system of  claim 12 , wherein the second output stage causes a first transistor in the first output stage to operate in a first saturation region.  
   
   
       23 . The IC output stage protection system of  claim 12 , wherein the at least one diodes comprises an NMOS device configured as a diode, said NMOS device having a guard ring coupled to first and second contacts on a P-substrate.