Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby

Abstract

Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

1 . A semiconductor integrated circuit comprising: 
 an inter-layer insulating layer stacked on a single-crystalline semiconductor substrate;    a single-crystalline semiconductor plug penetrating the inter-layer insulating layer; and    a single-crystalline semiconductor body formed on the inter-layer insulating layer,    wherein the single-crystalline semiconductor body has a single-crystalline epitaxial semiconductor pattern grown using the single-crystalline semiconductor plug as a seed layer and a semiconductor layer crystallized using a solid phase epitaxial technique that employs the single-crystalline epitaxial semiconductor pattern as a seed layer.    
   
   
       2 . The semiconductor integrated circuit according to  claim 1 , wherein the single-crystalline semiconductor plug is an epitaxial layer formed using an SEG technique that employs the single-crystalline semiconductor substrate as a seed layer.  
   
   
       3 . The semiconductor integrated circuit according to  claim 1 , wherein the crystallized semiconductor layer is a single-crystalline semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer.  
   
   
       4 . The semiconductor integrated circuit according to  claim 1 , further comprising a thin film transistor formed on the single-crystalline semiconductor body, wherein the thin film transistor has source and drain regions formed in the single-crystalline semiconductor body, the thin film transistor including a gate electrode extending across a channel region between the source/drain regions and covering sidewalls of the single-crystalline semiconductor body.  
   
   
       5 . The semiconductor integrated circuit according to  claim 1 , further comprising: 
 an isolation layer formed on a predetermined region of the single-crystalline semiconductor substrate to define an active region therein; and    a bulk metal oxide semiconductor (MOS) transistor formed in the active region,    wherein the bulk MOS transistor has source and drain regions formed in the active region, the bulk MOS transistor including a gate electrode extending across a channel region between the source/drain regions.    
   
   
       6 . The semiconductor integrated circuit according to  claim 5 , wherein the single-crystalline semiconductor plug is electrically coupled to any one of the source and drain regions of the bulk MOS transistor.  
   
   
       7 . A thin film transistor static random access memory (TFT SRAM) cell including first and second half-cells, each of the first and second half-cells comprising: 
 an isolation layer formed on a predetermined region of a single-crystalline semiconductor substrate to define an active region therein;    a driver transistor formed in the active region, the driver transistor having source and drain regions formed in the active region, the driver transistor further including a driver gate electrode extending across a channel region between the source and drain regions;    an inter-layer insulating layer overlying the driver transistor;    a single-crystalline semiconductor plug penetrating the inter-layer insulating layer to contact the drain region of the driver transistor; and    a single-crystalline semiconductor body formed on the inter-layer insulating layer and contacting the single-crystalline semiconductor plug,    wherein the single-crystalline semiconductor body has a single-crystalline enitaxial semiconductor pattern grown using the single-crystalline semiconductor plug as a seed layer, and a semiconductor layer crystallized using a solid phase epitaxial technique that employs the single-crystalline epitaxial semiconductor pattern as a seed layer.    
   
   
       8 . The TFT SRAM cell according to  claim 7 , wherein the single-crystalline semiconductor plug is an epitaxial layer formed using an SEG technique that employs the drain region of the driver transistor as a seed layer.  
   
   
       9 . The TFT SRAM cell according to  claim 7 , wherein the crystallized semiconductor layer is a single-crystalline semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer.  
   
   
       10 . The TFT SRAM cell according to  claim 7 , further comprising a load thin film transistor formed on the single-crystalline semiconductor body, 
 wherein the load thin film transistor has a load gate electrode extending across the single-crystalline semiconductor body and covering sidewalls of the single-crystalline semiconductor body, a drain region adjacent to the load gate electrode and located on the single-crystalline semiconductor plug, and a source region adjacent to the load gate electrode and located opposite to the drain region.    
   
   
       11 . The TFT SRAM cell according to  claim 10 , further comprising: 
 a second inter-layer insulating layer overlying the load thin film transistor;    a second single-crystalline semiconductor plug penetrating the second inter-layer insulating layer to contact the drain region of the load thin film transistor; and    a second single-crystalline semiconductor body formed on the second inter-layer insulating layer and contacting the second single-crystalline semiconductor plug,    wherein the second single-crystalline semiconductor body has a single-crystalline epitaxial semiconductor pattern grown using the second single-crystalline semiconductor plug as a seed layer and a semiconductor layer crystallized using a solid phase epitaxial technique that employs the single-crystalline epitaxial semiconductor pattern as a seed layer.    
   
   
       12 . The TFT SRAM cell according to  claim 11 , wherein the second single-crystalline semiconductor plug is an epitaxial layer formed using an SEG technique that employs the drain region of the load thin film transistor as a seed layer.  
   
   
       13 . The TFT SRAM cell according to  claim 11 , wherein the crystallized semiconductor layer is a single-crystalline semiconductor layer formed by crystallizing an amorphous semiconductor layer or a polycrystalline semiconductor layer.  
   
   
       14 . The TFT SRAM cell according to  claim 11 , further comprising a transfer thin film transistor formed on the second single-crystalline semiconductor body, 
 wherein the transfer thin film transistor has a transfer gate electrode extending across the second single-crystalline semiconductor body and covering sidewalls of the second single-crystalline semiconductor body, a source region adjacent to the transfer gate electrode and located on the second single-crystalline semiconductor plug, and a drain region adjacent to the transfer gate electrode and located opposite to the source region.    
   
   
       15 . The TFT SRAM cell according to  claim 14 , further comprising: 
 a third inter-layer insulating layer overlying the transfer thin film transistor; and    a node metal plug penetrating the first to third inter-layer insulating layers,    wherein the node metal plug is a metal layer having an ohmic contact with the drain region of the driver transistor, the single-crystalline semiconductor plug, the drain region of the load thin film transistor, the second single-crystalline semiconductor plug, and the source region of the transfer thin film transistor.    
   
   
       16 . The TFT SRAM cell according to  claim 14 , further comprising a transfer transistor formed in the active region and adjacent to the driver transistor, 
 wherein the transfer transistor has a transfer gate electrode extending across the active region as well as source and drain regions located on both sides of a channel region below the transfer gate electrode, respectively, and the source region of the transfer transistor corresponds to the drain region of the driver transistor.    
   
   
       17 . The TFT SRAM cell according to  claim 16 , further comprising: 
 a second inter-layer insulating layer overlying the load thin film transistor and the transfer transistor; and    a node metal plug penetrating the first and second inter-layer insulating layers, wherein the node metal plug is a metal layer having an ohmic contact with the drain region of the driver transistor, the single-crystalline semiconductor plug, and the drain region of the load thin film transistor.