Reduced power consumption for embedded processor

Abstract

An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.

1 . An embedded processor system, comprising: 
 at least one gated power unit;    said at least one gated power unit including an embedded non-volatile memory array; and    a power controller, receiving power via a system power signal, that provides at least one gated power signal to selectively provide power to said at least one gated power unit.    
   
   
       2 . The embedded processor system of  claim 1 , wherein said non-volatile memory array comprises a read-only memory (ROM).  
   
   
       3 . The embedded processor system of  claim 1 , further comprising: 
 an embedded processor coupled to said non-volatile memory array; and said power controller receiving a system clock signal and providing a gated clock signal to said processor to selectively control power consumption of said processor.    
   
   
       4 . The embedded processor system of  claim 3 , wherein said power controller performs a power down mode by first switching said gated clock signal to a static state to freeze said processor and then powering down each of said at least one gated power unit via said at least one gated power signal, and wherein said power controller performs a power up mode by first powering up each of said at least one gated power unit via said at least one gated power signal and then switching said gated clock signal to active to re-activate said processor.  
   
   
       5 . The embedded processor system of  claim 1 , further comprising: isolation circuitry coupled to at least one input and to at least one output of each of said at least one gated power unit that is operative to minimize current flow into each of said at least one gated power unit when powered down.  
   
   
       6 . The embedded processor system of  claim 5 , wherein said isolation circuitry comprises: 
 an input clamp circuit that selectively clamps said at least one input when said at least one gated power unit is powered down; and    an output isolation circuit that selectively isolates said at least one output when said at least one gated power unit is powered down.    
   
   
       7 . The embedded processor system of  claim 6 , wherein said output isolation circuit clamps a corresponding output signal to a known logic state when said at least one gated power unit is powered down.  
   
   
       8 . The embedded processor system of  claim 5 , wherein said isolation circuitry is controlled by said at least one gated power signal.  
   
   
       9 . The embedded processor system of  claim 1 , further comprising: 
 said at least one gated power unit including at least one static function; and    said power controller providing a first gated power signal to selectively provide power to said non-volatile memory array and providing a second gated power signal to selectively provide power to said at least one static function.    
   
   
       10 . An integrated circuit, comprising: 
 an embedded microprocessor;    a read-only memory (ROM) coupled to said embedded microprocessor, said ROM having a power input; and    a power control unit, receiving power via a system voltage signal, that provides a gated power signal to said power input of said ROM to selectively power up and power down said ROM.    
   
   
       11 . The integrated circuit of  claim 10 , further comprising: 
 said power control unit receiving a system clock signal and providing a gated clock signal to said microprocessor; and    said power control unit reducing power by placing said gated clock signal into a static state to place said microprocessor in idle mode and powering down said ROM by removing power from said gated power signal.    
   
   
       12 . The integrated circuit of  claim 11 , wherein said power control unit reactivates said microprocessor by first powering up said ROM by applying power to said gated power signal and then placing said gated clock signal to an active state.  
   
   
       13 . The integrated circuit of  claim 10 , further comprising: 
 at least one static function having a power input; and    said power control unit providing a second gated power signal to said power input of said at least one static function to selectively power up and power down said at least one static function.    
   
   
       14 . The integrated circuit of  claim 10 , further comprising isolation circuitry coupled to inputs and outputs of said ROM that minimizes current flow into said ROM when powered down.  
   
   
       15 . The integrated circuit of  claim 14 , wherein said isolation circuitry comprises: 
 at least one input clamp, each coupled to a corresponding input of said ROM, each input clamp clamping said corresponding input to minimize current flow when said ROM is powered down; and    at least one output isolation circuit, each coupled to a corresponding output of said ROM, each output isolation circuit isolating said corresponding output from powered devices when said ROM is powered down.    
   
   
       16 . The integrated circuit of  claim 14 , wherein said isolation circuitry is controlled by said gated power signal.  
   
   
       17 . A method of saving power in an embedded processor system having an embedded processor and an internal read-only memory (ROM), comprising: 
 selectively providing power to the ROM via a gated power signal; and    removing power from the ROM while the processor is in idle mode.    
   
   
       18 . The method of  claim 17 , further comprising: 
 providing a gated clock signal to the processor;    placing the processor in idle mode by placing the gated clock signal in a static state; and    said removing power from the ROM comprising removing power from the ROM after the processor is placed in idle mode.    
   
   
       19 . The method of  claim 18 , further comprising: 
 reactivating the processor by activating the gated clock signal; and    prior to said activating the gated clock signal, providing power to the ROM via the gated power signal.    
   
   
       20 . The method of  claim 17 , further comprising minimizing current flow into the ROM while powered down.  
   
   
       21 . The method of  claim 20 , wherein said minimizing current flow into the ROM while powered down comprises: 
 clamping inputs of the ROM; and    isolating outputs of the ROM.    
   
   
       22 . The method of  claim 17 , the embedded processor system including a static function, further comprising: 
 selectively providing power to the static function via a second gated power signal; and    removing power from the static function while the processor is in idle mode.